Memory Technology - Intro to Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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CS203A Computer Architecture

Lecture 15

Cache and Memory Technology

and Virtual Memory

Main Memory Background

• Random Access Memory (vs. Serial Access Memory)

• Different flavors at different levels

– Physical Makeup (CMOS, DRAM)

– Low Level Architectures (FPM,EDO,BEDO,SDRAM)

• Cache uses SRAM : Static Random Access Memory

– No refresh (6 transistors/bit vs. 1 transistor

Size : DRAM/SRAM 4-8 ,

Cost/Cycle time : SRAM/DRAM 8-

• Main Memory is DRAM : Dynamic Random Access Memory

– Dynamic since needs to be refreshed periodically

– Addresses divided into 2 halves (Memory as a 2D matrix):

• RAS or Row Access Strobe
• CAS or Column Access Strobe

Dynamic RAM

• SRAM cells exhibit high speed/poor density

• DRAM: simple transistor/capacitor pairs in

high density form

Word Line

Bit Line

C

Sense Amp

DRAM logical organization (4 Mbit)

• Square root of bits per RAS/CAS

Column Decoder

Sense Amps & I/O

Memory Array (2,048 x 2,048)

A0…A1 0

… 11

D

Q

Word Line

Storage Row Decoder Cell

…

• Access time of DRAM = Row access time + column

access time + refreshing

Main Memory Organizations

CPU

Cache

Bus

Memory

CPU

Bus

Memory

Multiplexor Cache

CPU

Cache

Bus

Memor y bank 1

Memory bank 2

Memory bank 3

Memory bank 0

one-word wide memory organization

wide memory organization interleaved memory organization

DRAM access time >> bus transfer time

Memory Interleaving

Interleaved memory is more flexible than wide-access memory in that it can handle multiple independent accesses at once.

Add-

ress

Addresses that

are 0 mod 4

Addresses that

are 2 mod 4

Addresses that

are 1 mod 4

Addresses that

are 3 mod 4

Return

data

Data

in

Data

(based onDispatch out

2 LSBs of

address)

Bus cycle Memory cycle

Module accessed

Time

Virtual Memory

• Idea 1: Many Programs sharing DRAM Memory so that context switches can occur
• Idea 2: Allow program to be written without memory constraints – program can exceed the size of the main memory
• Idea 3: Relocation: Parts of the program can be placed at different locations in the memory instead of a big chunk.
• Virtual Memory:

(1) DRAM Memory holds many programs running at same time (processes) (2) use DRAM Memory as a kind of “cache” for disk

Data movement in a memory hierarchy.

Memory Hierarchy: The Big Picture

Pages

Lines

Words

Registers

Main memory Cache

Virtual memory

(transferred

explicitly

via load/store) automatically(transferred

upon cache miss) automatically(transferred

upon page fault)

Mapping Virtual Memory to Physical Memory

• Divide Memory into equal sized “chunks” (say, 4KB each)

0

Physical Memory

∞

Virtual Memory

Heap

64 MB

0

• Any chunk of Virtual Memory assigned to any chunk of Physical Memory (“page”)

Stack

Heap

Static

Code

Single Process

Handling Page Faults

• A page fault is like a cache miss
  • Must find page in lower level of hierarchy
• If valid bit is zero, the Physical Page Number

points to a page on disk

• When OS starts new process, it creates

space on disk for all the pages of the process, sets all valid bits in page table to zero, and all Physical Page Numbers to point to disk

• called Demand Paging - pages of the process are loaded from disk only as needed

How to Perform Address

Translation?

• VM divides memory into equal sized pages
• Address translation relocates entire pages
  • offsets within the pages do not change
  • if make page size a power of two, the virtual address separates into two fields:
  • like cache index, offset fields

Virtual Page Number (^) Page Offset virtual address

Mapping Virtual to Physical Address

Virtual Page Number Page Offset

Physical Page Number Page Offset

Translation

31 30 29 28 27 .………………….12 11 10

29 28 27 .………………….12 11 10

9 8 ……..……. 3 2 1 0

Virtual Address

Physical Address

9 8 ……..……. 3 2 1 0

1KB page size

Address Translation: Page Table

Virtual Address (VA):

virtual page nbr offset

Page Table

Register

Page Table

is located

in physical

memory

index

into

page

table

Physical

Memory

Address (PA)

Access Rights: None, Read Only, Read/Write, Executable

Page Table

Val

-id

Access

Rights

Physical

Page

Number

V A.R. P. P. N.

0 A.R.

V A.R. P. P. N.

disk Docsity.com

Page Tables and Address Translation

The role of page table in the virtual-to-physical address translation process.