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L07 - Synchronization 1
2/26/
Synchronization, Metastability
and Arbitration
Due tonight:
^ Lab #
^ Lab #1 checkoff meeting
"If you can't be just,
be arbitrary"
Naked Lunch
Did you vote for Bush or Gore?
Didn’t have enough time to decide.
Well, which hole did you punch?
Both, but not very hard...
modified 2/23/09 09:
L07 - Synchronization 2
6.004 – Spring 2009
2/26/
The Importance of being Discrete
Digital Values:
Problem: Distinguishing voltages
representing “1” from “0” Solution:
Forbidden Zone:
avoid
using similar voltages for “1”and “0”
Digital Time:
Problem: “Which transition
happened first?” questions
Solution: Dynamic Discipline: avoid
asking such questions inclose races
V V OH V IH V IL V OL OUT
V IN
V OL
V IL
V IH
V OH
tS
tH
D ClkQ
tCDtPD
We avoid possible errors by disciplines that avoid asking the tough
questions – using a
forbidden zone
in both voltage and time dimensions:
L07 - Synchronization 3
2/26/
If we follow these simple rules…
Can we guarantee that our system will always work?With careful design we can make sure that the dynamic
discipline is obeyed everywhere*...
D Q
D Q
Out
In
Combinational
logic
D Q
Out
Combinational
logic
D Q
In Clk
Combinational
logic
D Q
Combinational
logic
D Q
Combinational
logic
D Q
Out
Combinational
logic
almost
everywhere...
L07 - Synchronization 4
6.004 – Spring 2009
2/26/
Which edge Came FIRST?
The world doesn’t run on our clock!
What if each button input is
an asynchronous 0/1level?
Lock
B
U
B
0 1
0 1
To build a system with asynchronous inputs, we have to break the rules:
we cannot guarantee that setup and hold time requirements are met at theinputs! So,
lets use a “synchronizer” at each input: 0 1
(Unsynchronized)
U(t)
S(t)(Synchronized)Clock
Synchronizer
Valid except for brief periodsfollowing active clock edges
But whatAbout theDynamicDiscipline?
L07 - Synchronization 5
2/26/
The Asynchronous Arbiter:
a classic problem
Arbiter
B C
S
B: C:
at t
B
at t
C
B: C: S:
tD
tD
t
E^
t
E
tD
Arbiter specifications: • finite t
D
(decision time)
finite t
E^
(allowable error)
value of S at time t
C +t
D
if t
B
< t
C^
E
if t
B
t
C^
E
otherwise
CASE 1
CASE 2
CASE 3
UNSOLVABLE
For NO finite valueof t
E^
and t
D
is this
spec realizable,even with reliablecomponents!
L07 - Synchronization 6
6.004 – Spring 2009
2/26/
Violating the Forbidden Zone
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. Ifthe red x still appears, you may have to delete the image and then insert it again.
tB
-t
C
ArbiterOutput^1 o
(t
B =t
C
B Earlier
C Earlier
Arbiter
B C
S
B: C:
at t
B
at t
C
Issue: Mapping the
continuous
variable (t
B
)C^
onto the
discrete
variable S in bounded time.
With no “forbidden zone,” all inputs have to bemapped to a valid output. As the inputapproaches discontinuities in the mapping, ittakes longer to determine the answer. Givena particular time bound, you can find an inputthat won’t be mapped to a valid outputwithin the allotted time.
L07 - Synchronization 7
2/26/
Unsolvable? that can’t be true...
Lets just use a D Flip Flop:
D
Q
B: C:
at t
B
at t
C
DECISION TIME
is T
PD
of flop.
ALLOWABLE ERROR
is max(t
SETUP
, t
HOLD
)
Our logic:T
PD
after T
, we’ll haveC
Q=0 iff t
B^
SETUP
< t
C
Q=1 iff t
HOLD
< t
B
Q=0 or 1 otherwise.
We’re lured by the digital
abstraction into assumingthat Q must be either 1 or 0.But lets look at the input latchin the flip flop when B and Cchange at about the sametime...
D G
Q
D G
Q
B C
master
slave
L07 - Synchronization 8
6.004 – Spring 2009
2/26/
The Mysterious Metastable State
V
in
V
out
VTC of
“closed” latch
VTC of feedback path (V
in =V
out
)
Latched ina ‘0’ state
Latched ina ‘1’ state
Latched inan undefined
state
Y
(^01)
Q
V
out
V
in
Recall that the latch output is the
solution to two simultaneousconstraints:
- The VTC of path thru
MUX; and
- V
in
= V
out
In addition to our expected stable solutions, we find an unstable
equilibrium in the forbidden zone called the “Metastable State”
L07 - Synchronization 13
2/26/
The Metastable State:
Why is it an inevitable risk of synchronization?
Our active devices always have a fixed-point voltage, V
M
, such that
V
IN
=V
M
implies V
OUT
= V
M
Violation of dynamic discipline puts our feedback loop at some voltageV
0
near V
M
The rate at which V progresses toward a stable “0” or “1” value isproportional to (V - V
M
The time to settle to a stable value depends on (V
0
- V
M ); its
theoretically infinite for V
0
= V
M
Since there’s no lower bound on (V
0
- V
M
), there’s no upper bound on
the settling time.
Noise, uncertainty complicate analysis (but don’t help).
L07 - Synchronization 14
6.004 – Spring 2009
2/26/
Sketch of analysis… I.
0 1
S(t)(Synchronized)Clock
Synchronizer
Assume asynchronous 0->1at T
A , clock period CP:
Whats the FF output voltage,V 0 , immediately after T
?A
A C
< t
+tS
H
CP
V
M
- Whats the probability that the
voltage, V
0 , immediately after
TA is within
of V
M
]
[^
0
L
H
H
S
M
V
V
CP
t
t
V
V
P
V
0
t
-tA
C
Potential trouble comes when V
0
is near the metastable point, V
M
…
L07 - Synchronization 15
2/26/
Sketch of analysis… II.
We can model our
combinationalcycle as anamplifier with gainA and saturationat V
, VH
L
0 A 1
V
out
V
in 0
R
C
V
H
V
L
Vout
Slope = AVin
- For V
out
near V
M
, V
out
(t) is an
exponential whose time constantreflects RC/A:
- Given interval T, we can compute a
minimum value of
= |V
0 -V
M | that will
guarantee validity after T:
V
out
(t)-
V
M
e
t(A-1)/RC
e
t/
(T)
(V
H
– V
M
) e -
T/
- Probability of metastability after T is
computed by probability of a V
0
yielding
(T) …
P
M
(T)
P[|V
0
-V
M
(T)]
K e -
T/
L07 - Synchronization 16
6.004 – Spring 2009
2/26/
Failure Probabilities vs Delay
Making conservative assumptions about the distribution of V
0
and system
time constants, and assuming a 100 MHz clock frequency, we get results likethe following:
Average time
Delay
P(Metastable)
between failures
31 ns
3x
1 year
33.2 ns
3x
10 years
100 ns
30
years!
[For comparision:
Age of oldest hominid fossil: 5x
6 years
Age of earth: 5x
9 years]
Lesson: Allowing a bit of settling time is an
easy way to avoid metastable states inpractice!
L07 - Synchronization 17
2/26/
The Metastable State:
a brief history
Antiquity: Early recognitionDenial: Early 70sFolk Cures: 70s-80sReconciliation: 80s-90s
Buriden’s Ass, and other fables…Widespread disbelief. Early analysesdocumenting inevitability of problemrejected by skeptical journal editors.Popular pastime: Concoct a “Cure” forthe problem of “synchronization failure”.Commercial synchronizer products.Acceptance of the reality:synchronization takes time. Interestingspecial case solutions.
L07 - Synchronization 18
6.004 – Spring 2009
2/26/
Ancient Metastability
Metastability is the occurrence of a persistent invalid
output… an unstable equilibria.
The idea of Metastability is not new:
The Paradox of Buridan’s Ass
Buridan, Jean (1300-58), French Scholastic philosopher,who held a theory of determinism, contending that thewill must choose the greater good. Born in Bethune, hewas educated at the University of Paris, where he studied withthe English Scholastic philosopher William of Ockham (whomyou might recall from his razor business). After his studies werecompleted, he was appointed professor of philosophy, and laterrector, at the same university. Buridan is traditionally, butprobably incorrectly, associated with a philosophical dilemma ofmoral choice called "Buridan's ass.”In the problem an ass starves to death between two alluringbundles of hay because it does not have the will to decide whichone to eat.
L07 - Synchronization 19
2/26/
Folk Cures
the “perpetual motion machine” of digital logic
FF
"FIXER"
delay
AsyncInput
"Clean"Output
Bad Idea # 1: Detect metastable state & Fix
Theimagecannot
Theimagecannot
Theimagecannot
valid"0"
valid "1"
Bad Idea #2: Define the problem away by making metastable point a valid output
Bug: detecting metastability isitself subject to metastablestates, i.e., the “fixer” will fail toresolve the problem in boundedtime. Bug: the memory element will flipsome valid “0” inputs to “1”after a while.
Many other bad ideas – involving noise injection,
strange analog circuitry, … have beenproposed.
L07 - Synchronization 20
6.004 – Spring 2009
2/26/
There’s no easy solution
… so, embrace the confusion.
"Metastable States":
- Inescapable consequence of bistable systems• Eventually a metastable state will resolve itself to valid binary
level.
- However, the recovery time is UNBOUNDED ... but influenced by
parameters (gain, noise, etc)
- Probability of a metastable state falls off EXPONENTIALLY with
time -- modest delay after state change can make it very unlikely. Our STRATEGY; since we can’t eliminate metastability, we will do the
best we can to keep it from contaminating our designs
L07 - Synchronization 25
2/26/
Every-day Metastability - I
Bit Bucket Cafe
The imagecannot bedisplayed.Yourcomputermay nothaveenoughmemoryto openthe image,
Ben Bitdiddle tries the famous“6.004 defense”:Ben leaves the Bit Bucket Caféand approaches fork in theroad. He hits the barrier in themiddle of the fork, laterexplaining “I can’t be expectedto decide which fork to take inbounded time!”.Is the accident Ben’s fault?
“Yes; he should have stopped until his decision
was made.”
Judge R. B. Trator, MIT ‘
L07 - Synchronization 26
6.004 – Spring 2009
2/26/
Every-day Metastability - II
GIVEN:
Normal traffic light:
GREEN, YELLOW, RED sequence
55 MPH Speed Limit
Sufficiently long YELLOW, GREEN periods
Analog POSITION input
digital RED, YELLOW, GREEN inputs
digital GO output
Can one reliably obey....
PLAUSIBLE STRATEGIES:
A. Move at 55. At calculated distance D from light, sample color (using an
unbounded-time synchronizer). GO ONLY WHEN stable GREEN. B. Stop 1 foot before intersection. On positive GREEN transition, gun it.
LAW #1: DON’T CROSS LINE while light is RED.
GO = GREEN
LAW #2: DON’T BE IN INTERSECTION while light is RED.
L07 - Synchronization 27
2/26/
Summary
As a system designer…
Avoid the problem altogether, where possible
Use single clock, obey dynamic discipline
Avoid state. Combinational logic has no metastablestates!
Delay after sampling asynchronous inputs: a
fundamental cost of synchronization
The most difficult decisions
are those that matter the least.
Image by MIT OpenCourseWare.
