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Guidelines for Working with i80186_hv Model in Microprocessors Course, Study Guides, Projects, Research of Microprocessors

San Diego State University (SDSU)Microprocessors

Guidelines for working with the i80186_hv model in compe 475 - microprocessors course. It includes revision history, directory structure, instructions for instantiating 80c186 model, creating pcl file, attaching program files, interconnecting microprocessor pins, adding pld/fpga, interconnecting pld/fpga and microprocessor, specification of ram contents, and copying/moving mentor graphics data. It also provides files to help with the project and a demo file to run from dmgr.

Typology: Study Guides, Projects, Research

Pre 2010

Uploaded on 03/28/2010

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CompE 475- Microprocessors
Guidelines for Working with i80186_hv Model
** Revision History **
Revised 04-06-04: Updated for the use of Altera CPLDs/FPGAs
Revised & Updated 11-30-03: Updated info on use of Xilinx devices, reformatted and edited information for correctness -KW
Revised 11-20-01: Updated item 5 (removed reference to S2 and added /PCS0) - NP
Revised 11-08-01: Updated info on simulation via Quicksim II
Revised 02-07-00: to include Am28F010 EEPROM and KM62256 SRAM.
Revised 11-17-99: Item 6: corrected mach221-10-com in mcf file contents.
(Revised 9-27-99)
(Revised 8-31-98)
(Revised item 3 on 2-16-98)
(Revised item 6 on 1-9-98)
Important Notes:
• Reference to "yourname" requires that you type in the name of your home folder.
• Also, it is not necessary to switch to Bus Ripper auto mode when in Design Architect.
Step1. Directory structure
Use the file manager to make a folder called 475proj under /home/student/yourname. Place your
schematic folder and your memory contents files, the .j1, .pcl, .mcf and .frc files under the 475proj
folder. See item 10 below for memory contents files. See item 3 below for .pcl file. See item 7 below for
.mcf file.
• After using the file manager to create the folder 475proj, define the MGC_WD variable for ease.
• Start design manager by typing dmgr &. Invoke Design Architect and click on open sheet.
• The top line of the requestor (Component Name) will probably indicate:
/home/student/yourname or /home/student/yourname/475proj.
• Edit the line to make it read: /user/student/yourname/475proj/project where “project” is the
name of the schematic that you will be creating or make up your own name for the schematic
(instead of project).
• This will put your new schematic under 475proj. 475proj is a folder to conveniently keep all
your files together and away from files for other projects. The name "project" is the name of your
schematic.
Step2. Instantiating 80C186 Model
In Design Architect choose the i80C186-16 HVM model (the BUS version is more convenient if you
know how to handle busses) as follows: Libraries
Æ
Logic Modeling SmartModel Library. Then in the
palette on the right choose:
Processor
Æ
Microprocessor
Æ
Intel
Æ
80C186 16-Bit Microprocessor
Æ
i80C186-16 HVM (Bus).
If necessary, place the the mouse pointer over the palette, press the right mouse button, and select "Resize
Palette" to allow you to read some of the long names. Place the model in your schematic by clicking the
left mouse button.
Step3. 80C186 Program File
Using Smartmodel Libraries the 80C186 program is created as a .pcl file (see online documentation for
more details). A blank pcl file for the i80C186 is in
/user/class/ee475/project.src
• Make a copy under your 475proj folder.
• To create the pcl file that controls what kinds of cycles the i80C186 runs, first calculate how
many wait periods each of your devices will require, then compile the bit patterns required for the
pf3
pf4
pf5

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CompE 475- Microprocessors

Guidelines for Working with i80186_hv Model

**** Revision History **** Revised 04-06-04: Updated for the use of Altera CPLDs/FPGAs Revised & Updated 11-30-03: Updated info on use of Xilinx devices, reformatted and edited information for correctness -KW Revised 11-20-01: Updated item 5 (removed reference to S2 and added /PCS0) - NP Revised 11-08-01: Updated info on simulation via Quicksim II Revised 02-07-00: to include Am28F010 EEPROM and KM62256 SRAM. Revised 11-17-99: Item 6: corrected mach221-10-com in mcf file contents. (Revised 9-27-99) (Revised 8-31-98) (Revised item 3 on 2-16-98) (Revised item 6 on 1-9-98)

Important Notes:

  • Reference to "yourname" requires that you type in the name of your home folder.
  • Also, it is not necessary to switch to Bus Ripper auto mode when in Design Architect.

Step1. Directory structure Use the file manager to make a folder called 475proj under /home/student/yourname. Place your schematic folder and your memory contents files, the .j1 , .pcl , .mcf and .frc files under the 475proj folder. See item 10 below for memory contents files. See item 3 below for .pcl file. See item 7 below for .mcf file.

  • After using the file manager to create the folder 475proj, define the MGC_WD variable for ease.
  • Start design manager by typing dmgr &. Invoke Design Architect and click on open sheet.
  • The top line of the requestor (Component Name) will probably indicate: /home/student/yourname or /home/student/yourname/475proj.
  • Edit the line to make it read: /user/student/yourname/475proj/project where “ project ” is the name of the schematic that you will be creating or make up your own name for the schematic (instead of project).
  • This will put your new schematic under 475proj. 475proj is a folder to conveniently keep all your files together and away from files for other projects. The name " project " is the name of your schematic.

Step2. Instantiating 80C186 Model In Design Architect choose the i80C186-16 HVM model (the BUS version is more convenient if you

know how to handle busses) as follows: Libraries Æ Logic Modeling SmartModel Library. Then in the

palette on the right choose:

Processor Æ Microprocessor Æ Intel Æ 80C186 16-Bit Microprocessor Æ i80C186-16 HVM (Bus).

If necessary, place the the mouse pointer over the palette, press the right mouse button, and select "Resize Palette" to allow you to read some of the long names. Place the model in your schematic by clicking the left mouse button.

Step3. 80C186 Program File Using Smartmodel Libraries the 80C186 program is created as a .pcl file (see online documentation for more details). A blank pcl file for the i80C186 is in /user/class/ee475/project.src

  • Make a copy under your 475proj folder.
  • To create the pcl file that controls what kinds of cycles the i80C186 runs, first calculate how many wait periods each of your devices will require, then compile the bit patterns required for the

UMCS, LMCS, MMCS, and PACS configuration registers of the 80C186, and then use the editor to edit and save project.src by adding correct values for the configuration register.

  • Change the memory access values for the read and write cycles to reflect your memory locations. Next, enter the following command in a unix terminal window compile_pcl project.src project.pcl
  • This produces the project.pcl file that the 80C186 model uses, and stores it in the 475proj directory.
  • For more information: see the Synopsys PCL Reference available at the class website

Step4. Attaching Program Files to Smartmodels

Select only the i80C186 model in your schematic and go to Properties Æ Modify ..., then select

PCLFile=..., click OK , and change the " value " field to the full pathname where you have put the project.pcl file (i.e., enter: /home/student/yourname/475proj/project.pcl ). Click OK to finish this step.

  • Do the same with the RAM and EPROM devices except change Memory File=... (see item 10 below)
  • Do the same with each of your PLD device, except change SCF File=... (see item 6 below)

Step5. Interconnecting the Microprocessor Pins The only signals that you need to connect on the microprocessor model 80C186 model are: NRES, X1, AD(15:0), A(19:16), /PCS0, /UCS, /LCS, ALE, /WR, /RD, and /BHE.

  • Note, do not use the "/" symbol when naming these signals on your schematic. Substitute "N" as in NRES, NUCS, NLCS, NWR, NRD, NBHE, NWEU, NWEL , etc.
  • All other signals can be left floating. Later when you invoke QuickSim it will complain but will assume correct default values. Your /reset input should be connected to /RES. Your CLK input should be connected to the X1 input.

Step6. Adding a Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA)

For each programmable smartmodel instance (programmable device) that uses a netlistFile SCF

attribute, make sure the attribute points at a MCF file, e.g.,

/home/student/yourname/475proj / xxx.mcf

The xxx.mcf file (ASCII file) should contain the following command line:

load -source < file_name >

where < file_name > is:

  • nnn.edo for Altera , QuickLogic, Cypress
  • nnn.xnf for Xilinx FPGA and nnn.jed for Xilinx CPLDs
  • nnn.adl or .def or .pin or .stf for Actel
  • nnn.sim for Lattice
  • nnn.jed for PLDs

1. Note, that the pin assignments in the schematic should correspond to the pin

assignments in the User Constraints when compiling a programmable device

using its native compiler.

2. When starting Quicksim, the -source command causes the model to load the

source netlist file specified by the < file_name > argument and, if necessary,

recompile the file.

(1) Check for a Model Messages box that will tell you whether any fuses were blown in your PLD. If it says zero, then there is a problem with your model. You will have to go back to Design Architect and correct the problem.

(2) Setup Æ Kernel Æ Analysis ...

  • In the requester, click on Visible, change Timing Mode to MAX, change Constraint Mode to MESSAGES. Also click on Contention Check and Model Messages, then OK.
  • This enables a special feature of the Logic Modeling devices. During any simulation you will get messages whenever any setup or hold time, frequency limit, or pulse width specs are violated. To see this in action run a simulation with a very small CLK period, like 15 NS, and you will see the Model Messages box filled with complaints, but the simulation will run anyway.
  • When defining forces, select Fixed or Wired forces for bidirectional I/O lines, otherwise your logic level input will be seen by Quicksim II as clashing with the high impedance level programmed for such a bidirectional output.
  • See /user/class/ee475/project.frc for a sample force file to be used to automate running traces in QuickSim. Copy this sample to your 475proj folder and use the editor to make changes to reflect your signal names. To get a trace move the mouse away from the menu and palette areas and just start typing: dofile project.frc to get a new set of traces.
  • A requestor box pops up automatically to receive this command. Execute the command by hitting the " enter " key on your keyboard.
  • Note, if you have to run the trace again, you will need to reset, select CLK and delete forces, then double-click the old trace window away and start typing the dofile command again. If this fails to erase the old traces, you might have to restart the Quicksim program.
  • Note: The reset function works OK by itself. Simply click the 'RESET ...' button in the palette on the right, choose the 'State' box, and if necessary click away the 'Save results Waveform DB' box (we DON'T want to save any results). Then click OK and it clears waveforms away from the Trace window (no need to click away the old Trace window). Now type in the dofile command to get a new set of waveforms.

Step 10. Specification of RAM Contents To specify the contents of any RAM or EEPROM locations simply use the text editor to enter data in the format HEX_ADDRESS/HEX_CONTENTS HEX_ADDRESS/HEX_CONTENTS etc. See /user/class/ee475/rom_upper and rom_lower for examples.

Step 11. Printing from Mentor Graphics Tools

To print a schematic from design architect, simply pull down the MGC Æ Setup Æ Printer menu and

highlight the line that reads: e-207-lj4mv Plot to mgcps

Click on the " Select Printer " button, and also click on 'landscape' under Orientation. Then, click ' OK ' to return to Design Architect. When you select the 'Print Sheet :' option thereafter, your schematic will be plotted on the HP-4MV printer in E-207 (check with Mr. Paolini or procedure to use a printer in room E220). The same procedure can be used in QuickSim. To print trace waveforms, select the trace window

and perform Files Æ Print Æ Active window

Step 12. Copying/Moving Mentor Graphics Data If you should have to move / copy an entire schematic do not use the file manager. There is file information embedded in the schematic files that only Design Manager can handle. In a terminal window, enter dmgr & to get into Design Manager, then find your schematic in the right hand window (use the arrow keys near the bottom to navigate through your folders). Schematics have a circuit graphic on them. Select the schematic and click COPY on the palette, then enter the full pathname where you want the schematic copied.