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Last (family) name: _________________________ First (given) name: _________________________ Student I.D. #: _____________________________ Department of Computer Sciences University of Wisconsin - Madison CS/ECE 752 Advanced Computer Architecture I
Midterm Exam 1
Monday, February 17, 2014
Instructions:
- Open book/open notes.
- The exam is multiple choice and will be graded using a separate automatically read grading sheet. Please write your name, ID number, and answers on the grading sheet. Be sure to fill in the bubbles fully for each question.
- Upon announcement of the end of the exam, stop writing on the exam paper immediately. Pass the exam to aisles to be picked up by the proctors. The instructor will announce when to leave the room.
- Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures. Problem Type Points Score 1 - 15 Multiple Choice 30 16 - 18 Hierarchical Branch Predictor Performance 15 19 - 23 Program Data Dependence Analysis 15 24 - 27 Instruction Scheduling 20 28 - 37 From the Readings 20 Total 100
Problems 1-20: (40 pts): Multiple choice; select the best answer for each question Note: Some of the answers below are “list” answers, such as “All of the above” and “Both (a) and (b).” In these answers, the word “above” refers only to “real” answers with specific content, not other list answers.
- A pipelined processor that does not have any WAR register hazards
- Must have an earlier register read stage and a later register write stage
- Must have an earlier register write stage and a later register read stage
- Must have two stages that write registers, one later than the other
- None of the above
- A VLIW instruction set processor
- Packs multiple operations into a single instruction
- Usually relies on software to resolve pipeline hazards
- Can operate at much higher frequency than other approaches
- Exposes a lot more instruction-level parallelism than other approaches
- Both (a) and (b)
- None of the above
- Local branch history in a dynamic branch predictor is used to:
- Predict a branch based on how neighboring branches were resolved recently
- Predict a branch based on how that same branch resolved recently
- Predict a branch based on the sign bit of its offset field
- Predict a branch based on a profiling run collected with a representative input set
- A branch that is mispredicted as not-taken requires the processor control logic to:
- Restart fetching instructions from the not-taken path
- Clear out all instructions that were not tagged with the mispredicted branch’s tag
- Fix up the rename table to correspond to the state following the branch
- None of the above
- Both (b) and (c)
- A two-level dynamic branch prediction:
- Uses a second-level branch history table to capture the branch working sets of very large programs that contain thousands of branches
- Uses two levels of branch confidence to identify easy-to-predict and hard-to- predict branches
- Learns more than one possible prediction for a static branch by using branch outcome history as part of the lookup index into the pattern history table
- Accurately predicts exits from loops that have iteration counts in the hundreds
- None of the above
- The return address stack (RAS):
- Pushes the return address whenever a call instruction is encountered
- Pops a return address for every return instruction
- Raises an exception when the stack overflows or underflows
- None of the above
- Both (a) and (b)
- All of the above
- Clustering an N-wide super scalar typically:
- Increases CPI and increases cycle time
- Increases CPI and decreases cycle time
- Decreases CPI and increases cycle time
- Decreases CPI and decreases cycle time
- Dynamic power has a
- Linear relationship with voltage
- Quadratic relationship with voltage
- Cubic relationship with voltage
- None of the above
- Reducing clock frequency
- Reduces dynamic power
- Reduces static power
- Reduces performance
- All of the above
- Both (a) and (b)
- Both (a) and (c)
- None of the above
Hierarchical Branch Predictors (15 points) Some highly-pipelined processors use a hierarchical branch prediction scheme, similar to how most modern processors now use hierarchical caches. These systems typically have a small, simple level-1 (L1) predictor (e.g., a branch target buffer) that can return a prediction within a single cycle. The second level-2 (L2) predictor is typically a much larger multilevel predictor (such as a the Alpha EV-8 direction predictor) that makes a much more accurate prediction, but requires two or more cycles to make the prediction. Both predictors are accessed for each branch. The processor uses the L1 predictor to begin speculative execution of the branch, but checks this prediction using the L2 predictor. If the L2 predictor disagrees with the L1, the branch is aborted and restarted using the L2 prediction. Assuming the L2 prediction is correct, the L1 misprediction penalty is much smaller than a full misprediction penalty. These hierarchical predictors can be better than a large single-level predictor because the latter may have a larger penalty on a correctly predicted branch. Consider a hierarchical predictor with the following performance: L1 Prediction L2 Prediction Stall Cycles Correct Correct 0 Correct Incorrect 11 Incorrect Correct 3 Incorrect Incorrect 8 Assume that one in 6 instructions are branch instructions and that the L1 and L2 predictions are independent. Assume that all branch prediction stalls directly impact performance (as they might in the MIPS 5 - stage pipeline). Thus we want to know the contribution to the CPI caused by branch mispredictions (i.e., the stall cycles per instruction). Assume the L1 predictor is right 80% of the time and the L2 predictor is right 95% of the time.
- How many stall cycles per instruction are due to either L1 or L2 mispredictions?
- 65
- None of the above
- Which case contributes the most to stall cycles per instruction?
- L1 Correct, L2 Correct
- L1 Correct, L2 Incorrect
- L1 Incorrect, L2 Correct
- L1 Incorrect, L2 Correct
- None of the above
- Which is more important?
- Improving the L1 predictor from 80% to 90% accurate?
- Improving the L2 predictor from 95% to 97% accurate?
- Reducing the penalty on L1 mispredict, L2 correct predict from 3 to 2 cycles?
- Reducing the penalty on L1 correct predict, L2 mispredict from 11 to 8 cycles?
Instruction Scheduling (20 points) Using the same pseudo-assembly language, but adding floating point (i.e., the “.d” suffix means double precision), the questions below involve instruction schedules. 1 lw.d F0 = mem[R2 + 0] 2 mult.d F3 = F0 * F 3 sw.d F3 mem[R2 + 0] 4 lw.d F4 = mem[R3 + 0] 5 mult.d F5 = F4 * F 6 sw.d F5 mem[R3 + 0] 7 add.d F6 = F3 + F 8 sw.d F6 mem[R4 + 0] Assume the standard MIPS 5 - stage (single-issue) pipeline plus separate pipes for floating point multiply and floating point add. All loads and stores use the integer pipeline and the floating- point pipeline does not have an “M” stage. Load-use delay is one cycle, regardless of which pipeline uses the result. Floating point multiply has 3 execute cycles and floating point add takes two execute cycles, and both are fully pipelined.
- On what cycle does instruction 8 store its value to memory?
- Cycle 13
- Cycle 14
- Cycle 15
- Cycle 16
- Cycle 17
- None of the above
- A compiler scheduler that is trying to reduce stalls might generate the following instruction schedule (using the instruction numbers):
- 1, 2, 3, 4, 5, 6, 7, 8
- 1, 2, 3, 4, 5, 7, 6, 8
- 1, 2, 3, 4, 7, 5, 6, 8
- 1, 4, 2, 5, 3, 6, 7, 8
- 1, 4, 7, 8, 2, 5, 3, 6
- None of the above
- The key source of stalls in this code sequence is:
- The depth of the floating point multiply pipeline
- The depth of the floating point add pipeline
- The load-use delay
- A maybe dependence
- None of the above
- If the instruction set were IA-64 instead of MIPS, we could reduce stalls using:
- An advanced load for instruction 1
- An advanced load for instruction 2
- A speculative load for instruction 1
- A speculative load for instruction 2
- None of the above
From the readings (20 points)
- In Moore’s classic paper semiconductor scaling, he predicted which of the following technologies might be made possible:
- Personal computers
- Cell phones
- Self-driving cars
- None of the above
- All of the above
- Moore also predicted that the maximum number of transistors per chip would double:
- Every 12 months
- Every 18 months
- Every 24 months
- None of the above
- In Wulf’s paper on Compilers and Com[uter Architecture, he argues that “the failure general- register machines to treat all their registers alike” violates the following property:
- Regularity
- Orthogonality
- Composability
- None of the above
- All of the above
- In Srinivasan, et al.’s paper on optimal pipeline depth, they argue that as the pipeline depth increases, the following changes also occur:
- FO4 per stage increases, average glitch factor increases
- FO4 per stage increases, average glitch factor decreases
- FO4 per stage decreases, average glitch factor increases
- FO4 per stage in decreases, average glitch factor decreases
- None of the above
- In Seznec, et al.’s paper on the Alpha EV-8 branch predictor, the authors argue that partial update is superior to full update because:
- It limits the number of strengthened counters on a correct prediction.
- It doesn’t steal a table entry if it can be avoided
- It utilizes space better.
- None of the above
- All of the above
- The Intel IA-64 instruction set includes the following features:
- A register stack to pass arguments to and return values from subroutines
- Support for full predication
- Register renaming to support software pipelined loops
- None of the above
- All of the above
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