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The George Washington University
School of Engineering and Applied Science Department of Electrical and Computer Engineering
SPRING 2004 ECE
Mid-Term Exam
_____________________________________________
NAME
QUESTION SCORE OUT OF
TOTAL /
Notes:
1. This exam is CLOSED books/notes.
2. Please show ALL work. Incorrect answers with no supporting
explanations or work will be given no partial credit. Correct answers
with no supporting explanations or work will be given no partial
credit (as appropriate to the solution).
3. If I can’t read or follow your solution, it is wrong, and no partial credit
will be given — BE NEAT!
4. Please indicate clearly your answer to the problem.
5. Some problems on this exam may have more than one correct answer.
These questions will be graded according to your ability to arrive at a
(single) solution. You are NOT required to indicate every possible
solution – one will suffice.
1) Match each of the words below with its definition.
A) design synthesis B) design verification C) single stuck-at (SSA) fault D) fault coverage E) fault simulation
F) exhaustive testing G) deterministic testing H) electromigration I) fault J) infant mortality
K) equivalence L) dominance M) fault collapsing N) propogation O) justification
H a failure mechanism (mode) characterized by current induced self-diffusion
L property of two faults where a test that detects one fault will also detect the other (non-reversible)
O controlling circuit logic to control a fault from a primary input
J failure of a circuit, often due to process variations, within a short time after manufacture
B testing of a circuit or design prior to its implementation
F applying all possible input patterns to the primary inputs of a combinational circuit
I a model that represents the effect of a failure by means of the change that is produced in the system signal
K property of two faults where every pattern that detects one fault also detects the other (reversible)
D the percentage of detectable faults in the circuit under test (CUT) which are detected by the test set
G applying generated test patterns to target a specific fault model of a circuit
N controlling circuit logic to observe a fault on a primary output
A automated transformation of a design from level of abstraction to another
E evaluation of circuit responses in the presence of virtual faults
M reducing the total number of faults which must be tested for a circuit
C represents a line in the circuit fixed to logic value 0 or 1
A
B H
E
F G
Z C
D (^) V
G
G
G
G
G
AND 0 1 x D D' OR 0 1 x D D' A A' 0 0 0 0 0 0 0 0 1 x D D’ 0 1 1 0 1 x D D’ 1 1 1 1 1 1 1 0 x 0 x x x x x x 1 x x x x x D 0 D x D 0 D D 1 x D 1 D D' D' 0 D’ x 0 D' D' D’ 1 x 1 D' D' D
∩ 0 1 x D D
0 0 φ 0 Ψ Ψ 1 φ 1 1 Ψ Ψ x 0 1 x D D’ D Ψ Ψ D D φ D' Ψ Ψ D’ φ D'
Step Operation Gate A B C D E F G H V Z 1 Initialization x x x x x x x x x x 2 PDCF G2 x x x x x x D’ x x x 3 D-drive G4 x x x x 1 x D’ x D’ x 4 D-Drive G5 x x x x 1 x D’ 0 D’ D’ 5 Justification H=0 0/x x/0 x x 1 1 D’ 0 D’ D’ 6 Justification F 0/x x/0 1/x x/1 1 1 D’ 0 D’ D’
Test Patterns: 10101, 00101, 01101, 10011, 00011, 01011, 10111, 00111, 01111
4) How would you use IDDQ testing to determine that P2 is stuck on?
Explain and demonstrate. (5 pts.)
A
B
p1 p
n
n
Z
A B Result
1 1 Iddq
By applying this set of test vectors, the presence of the fault is
detected by the unusual current flow between Vdd and GND,
caused by the fact that p2 is stuck on and acting as a resistive
voltage drop. (Note: This test is NOT used to “identify” which gate
is at fault, but simply to indicate that a fault “exists”.)
