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ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
LECTURE 160 – MOSFET OP AMP DESIGN
(READING: GHLM – 472-480, AH – 269-286)
INTRODUCTION
Objective
The objective of this presentation is: 1.) Develop the design equations for a two-stage CMOS op amp 2.) Illustrate the design of a two-stage CMOS op amp Outline
- Design relationships
- Design of Two Stage CMOS Op Amp
- Summary
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
OP AMP DESIGN
Unbuffered, Two-Stage CMOS Op Amp
+
v (^) in
M1 M
M3 M
M
M
M
vout
V (^) DD
V (^) SS
VBias
+
C (^) c
C (^) L
Fig. 160-
Notation:
Si =
Wi Li =^ W/L^ of the ith transistor
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Design Relationships for the Two-Stage Op Amp
Slew rate SR =
I 5
Cc (Assuming^ I^7 >> I^5 and^ CL^ >^ Cc )
First-stage gain Av 1 =
g (^) m 1 gds 2 + gds 4 =^
2 g (^) m 1 I 5 ( λ 2 + λ 4 )
Second-stage gain A (^) v 2 =
g (^) m 6 gds 6 + gds 7 =^
g (^) m 6 I 6 ( λ 6 + λ 7 )
Gain-bandwidth GB =
gm 1 Cc
Output pole p 2 =
− gm 6 CL
RHP zero z 1 =
gm 6 Cc 60° phase margin requires that gm 6 = 2.2 gm 2 ( CL / Cc ) if all other roots are ≥ 10 GB.
Positive ICMR V in(max) = VDD −
I 5
β 3 −^ | VT 03 |(max) +^ VT 1(min))
Negative ICMR V in(min) = VSS +
I 5
β 1 +^ V^ T 1(max) +^ V^ DS 5 (sat)
Saturation voltage V (^) DS (sat) =
2 I DS
β (all transistors are saturated)
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters are given.
- Gain at dc, Av (0)
- Gain-bandwidth, GB
- Phase margin (or settling time)
- Input common-mode range, ICMR
- Load Capacitance, CL
- Slew-rate, SR
- Output voltage swing
Power dissipation, P diss
+
v (^) in (^) M1 M
M3 M
M
M
M
v (^) out
V (^) DD
V (^) SS
VBias
+
Cc
CL
V (^) SG 4
Max. ICMR and/or p 3
V (^) SG 6 +
V (^) out(max)
I 6
g (^) m 6 or Proper Mirroring V (^) SG 4 = V (^) SG 6
C (^) c ≈ 0.2 C (^) L (PM = 60°)
GB = (^) Cg^ m (^) c^1
Min. ICMR I 5 I 5 = SR·C (^) c (^) V out(min)
Fig. 160-
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Unbuffered Op Amp Design Procedure - Continued
- Check gain and power dissipation specifications.
Av =
2 g (^) m 2 g (^) m 6 I 5 ( λ 2 + λ 3 ) I 6 ( λ 6 + λ 7 ) Pdiss^ =^ ( I^5 +^ I^6 )( VDD^ +^ | VSS |)
- If the gain specification is not met, then the currents, I 5 and I 6 , can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power dissipation is too high, then one can only reduce the currents I 5 and I 6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings.
- Simulate the circuit to check to see that all specifications are met.
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
Example 1 - Design of a Two-Stage Op Amp
Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1μm.
Av > 3000V/V VDD = 2.5V VSS = -2.5V 60° phase margin GB = 5MHz CL = 10pF SR > 10V/μs Vout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I 5.
I 5 = (3x10-12)(10x10^6 ) = 30 μA
3.) Next calculate ( W / L ) 3 using ICMR requirements.
( W / L ) 3 =
30x10- (50x10-6)[2.5 − 2 − .85 + 0.55]^2 = 15^ →^ ( W / L )^3 =^ ( W/ L)^4 = 15
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Example 1 - Continued
4.) Now we can check the value of the mirror pole, p 3 , to make sure that it is in fact
greater than 10 GB. Assume the Cox = 0.4fF/μm^2. The mirror pole can be found as
p 3 ≈
- g (^) m 3 2 Cgs 3 =^
- 2 K ’ p S 3 I 3 2(0.667) W 3 L 3 C (^) ox = 2.81x^ (^9) (rads/sec)
or 448 MHz. Thus, p 3 , is not of concern in this design because p 3 >> 10 GB.
5.) The next step in the design is to calculate g (^) m 1 to get
gm 1 = (5x10^6 )(2π)(3x10-12) = 94.25μS
Therefore, ( W / L ) 1 is
( W/L ) 1 = ( W / L ) 2 =
g (^) m 12 2 K’ (^) N I 1 =
(94.25)^2
2·110·15 = 2.79^ ≈^ 3.0^ ⇒^ ( W/L )^1 = ( W / L )^2 =^3
6.) Next calculate V (^) DS 5 ,
VDS 5 = (−1) − (−2.5) −
30x10- 110x10-6·3 - .85 = 0.35V Using V (^) DS 5 calculate ( W / L ) 5 from the saturation relationship.
( W / L ) 5 =
2(30x10-6) (110x10-6)(0.35)^2 =^ 4.49^ ≈^ 4.5^ →^ ( W/L )^5 = 4.
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
| Example 1 - Continued
7.) For 60° phase margin, we know that
gm 6 ≥ 10 gm 1 ≥ 942.5μS
Assuming that g (^) m 6 = 942.5μS and knowing that g (^) m 4 = 150μS, we calculate ( W / L ) 6 as
( W / L ) 6 = 15
942.5x10 - (150x10-6) = 94.25^ ≈^94
8.) Calculate I 6 using the small-signal gm expression:
I 6 =
(942.5x10-6)^2 (2)(50x10-6)(94.25) = 94.5μA ≈ 95μA
If we calculate ( W / L ) 6 based on Vout (max), the value is approximately 15. Since 94
exceeds the specification and maintains better phase margin, we will stay with ( W / L ) 6 = 94 and I 6 = 95μA.
With I 6 = 95μA the power dissipation is
Pdiss = 5V·(30μA+95μA) = 0.625mW.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Design of the Nulling Resistor (M8)
In order to place the zero on top of the second pole ( p 2 ), the following relationship must
hold
Rz =
g (^) m (^6)
CL + Cc Cc =^
Cc + CL Cc
2 K’ P S 6 I 6
The resistor, Rz , is realized by the transistor M8 which is operating in the active region
because the dc current through it is zero. Therefore, R (^) z , can be written as
Rz =
∂ vDS 8 ∂ i (^) D 8
V (^) DS 8 =
K’ P S 8 ( V SG 8 -| V TP |)
The bias circuit is designed so that voltage VA is equal to V (^) B.
∴ | VGS 10 | − | VT | = | VGS 8 | − | VT |⇒ V (^) SG 11 = V (^) SG 6 ⇒
W 11
L 11 =^
I 10
I 6
W 6
L 6
In the saturation region
| VGS 10 | − | VT | =
2( I 10 )
K ' P ( W 10 / L 10 ) =^ | VGS^8 |^ −^ | VT |
∴ Rz =
K’ PS 8
K’ PS 10
2 I 10 =
S 8
S 10
2 K’ P I 10
Equating the two expressions for Rz gives
W 8
L 8 =^
Cc CL + Cc
S 10 S 6 I 6
I 10
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
Example 2 - RHP Zero Compensation
Use results of Ex. 1 and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p 2. Use device data given in Ex. 1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I 10. The first step in this design is to establish the bias components. In order to set VA equal to VB , then VSG 11 must equal VSG 6. Therefore,
S 11 = ( I 11 / I 6 ) S 6 Choose I 11 = I 10 = I 9 = 15μA which gives S 11 = (15μA/95μA)94 = 14.8 ≈ 15. The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1. There must be sufficient supply voltage to support the sum of V (^) SG 11 , VSG 10 , and VDS 9. The ratio of I 10 / I 5 determines the ( W / L ) of M9. This ratio is
( W / L ) 9 = ( I 10 / I 5 )( W / L ) 5 = (15/30)(4.5) = 2.25 ≈ 2
Now ( W / L ) 8 is determined to be
( W / L ) 8 =
3pF 3pF+10pF
1·94·95μA 15μA = 5.63^ ≈^6
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Example 2 - Continued
It is worthwhile to check that the RHP zero has been moved on top of p 2. To do this,
first calculate the value of Rz. VSG 8 must first be determined. It is equal to VSG 10 , which is
V SG 10 =
2 I 10
K’ PS 10 + | VTP | =^
50·1 + 0.7 = 1.474V
Next determine R (^) z.
Rz =
K’ P S 8 ( V SG 10 -| V TP |) =^
50·5.63(1.474-.7) = 4.590kΩ
The location of z 1 is calculated as
z 1 =
(4.590 x 10^3 )(3x10-12) −
3x10- 942.5x10-
= -94.46x10 6 rads/sec
The output pole, p 2 , is
p 2 =
942.5x10- 10x10-12^ = -94.25x^
(^6) rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved from the RHP to the LHP.
The results of this design are summarized below. W 8 = 6 μm W 9 = 2 μm W 10 = 1 μm W 11 = 15 μm
Lecture 160 – MOSFET Op Amp Design (1/30/04) Page 160-
SUMMARY
Programmability of the Two-Stage Op Amp
The following relationships depend on the bias current, Ibias , in the following manner and allow for programmability after fabrication.
Av (0) = gmIgmIIRIRII ∝
IBias
GB =
gmI Cc ∝^ IBias
Pdiss = ( VDD +| VSS |)(1+ K 1 + K 2 ) IBias ∝ Ibias
SR =
K 1 IBias Cc ∝^ IBias
Rout =
2 λ K 2 IBias ∝^
IBias
| p 1 | =
gmIIRIRIICc ∝^
IBias^2 IBias ∝ IBias 1.
| z | =
gmII Cc ∝^ IBias
Illustration of the Ibias dependence →
+
v (^) in
M1 M
M3 M
M
M
M
v (^) out
V (^) DD
V (^) SS
IBias
Fig. 160-
K 1 IBiasK^2 IBias
103 102
100
101
10 - 10-^2 10-^3 1 10 100 IBias IBias(ref)
Pdiss and SR^ | p^1 |
GB and z
Ao and Rout
Fig. 160-
