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351CS31 – COMPUTER ORGANIZATION AND ARCHITECTURE Explain the concept and real time uses of the various C++ file I/O classes and functions
Typology: Schemes and Mind Maps
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A C++ class is a collection of data and the methods necessary to control and maintain data. C++ supports a rich set of I/O functions and operations. These functions use the advanced features of C+
In a computer system, CPU and an I/O interface are designed independently of each other. When internal timing in each unit is independent from the other and when registers in interface and registers of CPU uses its own private clock. In that case the two units are said to be asynchronous to each other. CPU and I/O device must coordinate for data transfers. METHODS USED IN ASYNCHRONOUS DATA TRANSFER Strobe Control: This is one way of transfer i.e. by means of strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur. Handshaking: This method is used to accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. HANDSHAKING In case of source initiated data transfer under strobe control method, the source unit has no way of knowing whether destination unit has received the data or not. Similarly, destination initiated transfer has no method of knowing whether the source unit has placed the data on the data bus. Handshaking mechanism solves this problem by introducing a second control signal that provides a reply to the unit that initiate the transfer. There are two control lines in handshaking technique: Source to destination unit Destination to source unit SOURCE INITIATED TRANSFER Handshaking signals are used to synchronize the bus activities. The two handshaking lines are data valid , which is generated by the source unit, and data accepted , generated by the destination unit. The timing diagram shows exchange of signals between two units.
The sequence of events: The source unit initiates the transfer by placing the data on the bus and enabling its data valid signal. The data accepted signals is activated by the destination unit after it accepts the data from the bus. The source unit then disables its data valid signal, which invalidates the data on the bus. The destination unit the disables its data accepted signal and the system goes into its initial state.
Employs special bits which are inserted at both ends of the character code Each character consists of three parts; Start bit; Data bits; Stop bits. A character can be detected by the receiver from the knowledge of 4 rules; When data are not being sent, the line is kept in the 1-state (idle state) The initiation of a character transmission is detected by a Start Bit, which is always a 0 The character bits always follow the Start Bit After the last character, a Stop Bit is detected when the line returns to the 1-state for at least 1bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect.
Transmitter Register Accepts a data byte (from CPU) through the data bus Transferred to a shift register for serial transmission Receiver Receives serial information into another shift register Complete data byte is sent to the receiver register Status Register Bits Used for I/O flags and for recording errors Control Register Bits Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits Block Diagram
Transfer of data between a fast storage device and memory is limited by the speed of CPU Remove CPU from the path of communication and the technique is DMA DMA controller takes over the buses to manage the transfer directly between the I/O device and memory Bus Request (BR) – used by the DMA controller to request the CPU to relinquish control of the buses CPU activates bus grant to inform the external DMA that the buses are in high impedance state Burst transfer – block sequence consisting of memory words is transferred in a continuous bus when DMA controller is the master Cycle Stealing – allows DMA controller to transfer one data word at a time after which it must return control of the buses to the CPU Input Output Processor Processor with DMA capability that communicates with I/O devices IOP takes care of input and output tasks relieving the CPU from the housekeeping chores involved in I/O transfers IOP can fetch and execute its own instructions IOP instructions are specifically designed to facilitate I/O transfers
CPU – IO Processor Communication
