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Base Registers
This lecture is the first of two on Chapter 6 of Peter Abel’s textbook. Today, we cover the use of base registers in address calculation. Topics for today include.
- A review of 32–bit binary arithmetic, as described by IBM.
- A characterization of the sixteen general–purpose registers in the System/370. Which are really general purpose?
- Control sections and their relation to address calculation.
- Base register addressing. Computing effective addresses.
- Assigning and loading base registers.
- Instruction formats and the use of base registers.
32–bit binary arithmetic, as described by IBM.
The System/370 uses 32–bit two’s–complement signed integers. The range of these integers is – 31 to 2 31
- 1, inclusive. Now, 2 31 = 2,147,483,648, so the range is –2,147,483,648 through 2,147,483,6647. Each of the sixteen general–purpose registers contains binary integer data. The bits in the registers are numbered left to right. Notice that this is not the standard used in other courses. Bit 0 is the sign bit. It is 1 for a negative number and 0 for a non–negative. In the book’s terminology, “bits 1–31 are data”. This is not the way I would say it, but it is the terminology we shall use for this course. Addressing The general purpose registers perform all the addressing involved in referencing main storage. When used for addressing, the register is called a base register. When so used, the contents of the register are viewed as an unsigned integer. Some System/370 systems provide only 24 bits for addressing. Current System/390 systems use 64–bit addressing.
Register Naming Conventions
Note that there are two ways of writing the part of the standard prefix code. What we have discussed in these slides: *BALR 12, 0 USING , 12 What we have used in our labs: *BALR R12, 0 USING , R From this I infer that the assembler will accept either notation in places in which the syntax expects a register to be used. NOTE: The first line is a truncated subroutine call. The instruction says: 1. Store the address of the next instruction into R
- Branch to the address in the second argument. Since that second address is 0, the branch is not taken and execution continues.
CSECT: Control Sections
By definition, a control section (CSECT) is “a block of coding that can be relocated (independent of other coding) without altering the operating logic of the program”. For the modern programmer, a CSECT might be considered as an independent code module or package. The match in terminology is not precise, but suggestive. Very large assembly language programs will require more than one control section. [My note: This is probably old information.] In any case, the programs we write will require only one CSECT, even assuming the addressing constraints imposed by the old System/370 architecture. A program with a single CSECT may be started in one of two ways. For example, the program LAB01 may be started in one of two ways. LAB01 START LAB01 CSECT The assembler allows for the specification of a load address in the START or CSECT. This is probably a bad idea; it may be ignored by a modern operating system.
More on Register 0 As a Base Register
The bottom line is “Don’t try this (at home)”. In other words, any attempt to use register 0 for anything other than temporary results is likely to cause problems.
As noted above, some addresses are given in the form | B | D D D | , where
B is a hexadecimal digit indicating a base register, and
D D D is a set of three hexadecimal digits indicating an offset in the range 0 – 4095.
If the object code generated has the form | 0 | D D D | , then no base register is used in
computing the address. We shall use this later to load registers with positive constants. One has another option that might force register 0 to be a base register. We can start the program as follows. *BALR R0, 0 USING , R While this MIGHT assemble correctly (I have no idea), it is most certainly a very bad idea. Any call to a system procedure will disrupt the addressing.
Options: No Base Register vs. The Default Base Register
So far, we have considered only the object code form of a typical address. We now “jump ahead” a bit and look at two typical instructions that use this address type. One type of instruction, called “RS”, used for register–to–storage instructions. Such an instruction has source code of the form OP R1,R3,D2(B2). Such an instruction has object code of the form OP R 1 R 3 B 2 D 2 D 2 D 2. We look at LM , an interesting example of this format. LM R1,R3,S2 loads multiple registers in the range R1 – R3 from the memory
location specified by S2 , the address of which will be in the form | B 2 | D 2 D 2 D 2 |.
We now interpret the following code fragment. *BALR R12, 0 Establish register R12 (X‘C’) USING , R12 as the default base resister. LM R5,R7,S2 might have object code 98 57 C1 00. This uses the default base register. LM R9,R11,S3(R3) might have object code 98 9B 32 00. Object code such as 98 9B 0E 00 would call for use of an absolute address, not computed from a base register. For this example, it is likely to be bad code.
Base Register/Displacement Addressing: Relocating the Code
The second major advantage of base/displacement addressing still applies today. “The system facilitates program relocatability. Instead of assigning specific [fixed] storage addresses, the assembler determines each address relative to a base address. At execute time [after the program is loaded], the base address, which may be anywhere in storage, is loaded into a base register.” The standard prefix code *BALR 12, 0 USING , 12 may be translated as follows:
- What is my address?
- Load that address into register 3 and use it as an base address in that register. The other option for relocating code is to use a relocating loader to adjust fixed address references to reflect the starting address of the code. This is also acceptable.
In the 1960’s, code that did not reference absolute addresses was thought to be superior. It was called “position independent code”.
Addressing: More Discussion
Here are some more examples of addressing using an index register and a base register. All of these examples are taken from type RX instructions, which use indexing. Each of these is a four–byte instruction of the form OP R1,D2(X2,B2). The format of the object code is OP R 1 X 2 B 2 D 2 D 2 D 2. Each byte contains two hexadecimal digits. We interpret the 32–bit object code as follows. OP This is an eight–bit operation code. R 1 X 2 This byte contains two hexadecimal digits, each of which is significant. R 1 denotes a register as the source or destination of the operation. X 2 denotes a general–purpose register to be used as an index register. B 2 D 2 D 2 D 2 This contains the argument address as a base register and displacement. Remember that the displacement, given by three hexadecimal digits, is treated as a 12–bit unsigned integer. In decimal, the limit is 0 Displacement 4095. The general form by which an address is computed is Contents (Base Register) + Contents (Index Register) + Displacement. Some instructions do not use index register addressing.
Addressing: Example 1
Here is some object code for analysis. 58 40 C1 23 The first thing to note is that the opcode, 58 , is that for L , a Register Load. This is a type RX instruction with object code of the form OP R 1 X 2 B 2 D 2 D 2 D 2. As noted above, OP = 58. We see that R 1 = 4. It is register 4 that is being loaded from memory. We see that X 2 = 0. Indexed addressing is not used. We also note that B 2 D 2 D 2 D 2 = C1 23 , indicating an offset of X‘123’ from the address value stored in general–purpose register 12 (hexadecimal C ). Suppose that the value in general–purpose register 12 is X‘2500’. The effective address for this instruction is then X‘2500’ + X‘123’ = X‘2623’.
An Aside: When Is It NOT An Address?
Let’s look at the standard form used for a base & displacement address.
| B | D D D |
Technically, the 12–bit unsigned integer indicated by D D D is added to the contents
of the register indicated by B , and the results used as an address.
There are instructions in which the value so computed is just used as a value and not as an address. Consider the instruction SLL R4,1. It is assembled as shown below. 000018 8940 0001 00001 48 SLL R4, The base register is 0, indicating that no base register is used. The “offset” is 1. The value by which to shift is given as the sum, which is 1. We could use a standard register to hold the value of the shift count, as in the following, which uses R8 to hold the shift count. 000018 8940 8000 00001 48 SLL R4,0(R8) NOTE: This is a good example of not using a “base register” in order to generate an “absolute constant”, not relative to any address. Here, the value is a count.
Assigning and loading base registers.
If the program is to use a base register for base register/displacement addressing, that register must be specified and provided with an initial value. Again, the standard prefix code handles this. *BALR 12, 0 USING , 12 If register 12 is used as a base register, it cannot be used for any other purpose. In other words, your code should not reference register 12 explicitly. We have two standards suggested for a base register. The textbook uses register 3 and one of our examples uses register 12. Pick one and use it consistently.
Instruction Formats
There are six instruction formats of interest to us. These are classified by the type of transfer. RR Register to register transfers. RS Register to storage and register from storage RX Register to indexed storage and register from indexed storage SI Storage immediate SS There are two variants of these Storage to storage transfer instructions.
