Notes on Introducing CoolRunner-II Technology and Architecture | ETEC 373, Study notes of Digital Systems Design

Download Notes on Introducing CoolRunner-II Technology and Architecture | ETEC 373 and more Study notes Digital Systems Design in PDF only on Docsity!

CoolRunner™-II^ Technology &Architecture

Introducing CoolRunner-II • 0.18μ^ process technology • System voltage integration • Advanced design features– Multiple I/O standards and I/O banks– Input hysteresis– Extra clocking modes • Architecture allows design flexibility • Ultra low power using RealDigital technology • Allows CoolRunner full-CMOS circuitry to run at extremelylow power without compromising performance Quick Start Training

Quick Start Training

Function Block • 16 macrocells available • 40 true and complement input signals from AIM • Global signals available at macrocell • Product terms add more clocks, OEs, S/Rs • Product term sharing allows very high fit rate • PLA architecture features excellent pinlocking

Function Block ArchitectureQuick Start Training

(^40) From AIM^ PLA Array40x56^56 ProductTerms

MC 1 Feedback to AIM^ To I/O Block^16 MC 16^3 GlobalGlobalClocksSet/Reset

I/O Block CharacteristicsQuick Start Training

V^ for Local BankREF^ HSTL & SSTL VCCIO VREF^ I/O Pin Input Hysteresis^ 3.3V - 1.5V Input

I/O Pin to AIM

128 macrocell and larger devices to Macrocell (Direct Input)^ Slewrate^ from Macrocell^ Enabled^ Control Term^ PTB^ GTS[0:3]^ CGND^ Open Drain^ Disabled

Weak Pullup/BusHold VCCIO 4 /

Quick Start Training

Reducing Power • Icc = C x V x f + I^ ddq • To reduce power: – Lower capacitance – Lower voltage – Lower frequency

0.18 m lowers capacitance Low VCC @ 1.8V How can we reduce the frequency?

TraditionalSenseAmpDesigns

1.8 Volt (est)^ 2.5 Volt3.3 Volt^ Frequency

~ 200MHz

~ 200mA^ Icc^ ~ 100mA^ Note: 128 MC device estimate

DualEDGE Flip Flops Advantages: • Distribute divided clock^ globally

then double^ locally

at macrocell

–^ Decrease Icc on global clock nets • Use 2x clocking for double data rate (DDR) applications • No additional insertion delay

PTC GCK CLK CTPTC

D/T/L^ Q^ to I/O^ D^ T FFLatchDualEDGE^9 CE 3 Quick Start Training

Quick Start Training

CoolCLOCKDeviceDeviceInput Clock Input ClockRoutingRoutingDivideDivide

MacrocellMacrocell DIV2 GCK2 SyncReset

MCClockInputs Divideby 2

D/T/L^ Q^ D^ T LatchDualEDGE^9 GlobalDividedClock

500mV Input Hysteresis • Supports simple oscillation schemes • Ideal for slow edge rate, noisysignals^ –^ Analog comparators & sensors^ –^ Hall effect switches^ –^ IR inputs^ –^ R/C oscillators • Eliminate external Schmitt triggerbuffers • Reduces power consumption withslow signals Quick Start Training

V^ CoolRunner-II _In^ +

I/O Performance & FlexibilityQuick Start Training

XC2C32^ XC2C64^ XC2C

XC2C256^ XC2C384^ XC2C

I/O Banks^1

1 2

2 4 4

LVTTL 33*LVCMOS 33, 25, 18, 15SSTL3_I, SSTL2_I, HSTL_IInput Hysteresis Option  Slew Rate ControlCoolCLOCKDataGATE^  DualEDGE flip flopClock DividerBus Hold outputHot Pluggable

^    

  ^ 

^ ^

 ^ ^ 

* 1.5V inputs need hysteresis

CoolRunner-II Family Overview^ Features^ * Note: T speeds are preliminary and 1.5V inputs need hysteresisQuick Start Training

XC2C^

XC2C64^ XC2C128 XC2C256 XC2C384 XC2C

Macrocells^

F^ (MHz)^ Toggle^

F^ (MHz)^ SYSTEM^

Max I/O^

I/O Banks^

LVCMOS, LVTTL 1.5, 1.8, 2.5, 3.

Yes^ Yes^

Yes^ Yes^ Yes

Yes HSTL, SSTL^

No^ No^ Yes^

Yes^ Yes^ Yes DataGATE, DualEDGE^

No^ No^ Yes^

Yes^ Yes^ Yes Standby Power (uW)^

28.80^ 30.60^ 34.

37.80^ 41.^

Multiple Levels of Security

Yes^ Yes^

Yes^ Yes^ Yes

Yes

Packages (size, type)VQ44^ (10 x 10mm, leaded)^

PC44^ (16.5 x 16.5mm, leaded)

CP56^ (6 x 6mm, chip scale)

VQ100 (14 x 14mm, leaded)

CP132 (8 x 8mm, chip scale)

TQ144 (20 x 20mm, leaded)

PQ208 (28 x 28mm, leaded)

FT256 (17 x 17mm, BGA)

Maxium User I/O^184 212 PD

Quick Start Training

CPLD Software • CoolRunner-II Software support– ISE WebPACK 5.2i– WebFITTER– Full feature support • All Xilinx CPLDs supported! – CoolRunner-II– CoolRunner XPLA3– XC9500/XL/XV^ http://www.xilinx.com/ise

CoolRunner-II Technology

Summary

•^ Silicon performance of Xilinx FPGAs with the single-chipintegration of CPLDs •^ Architecture combines 9500-style macrocell withXPLA3’s PLA for best silicon/software efficiency •^ Industry leadership in:^ –^ High performance^ –^ I/O standards^ –^ Clock management capability^ –^ Low-power features •^ Uncompromised performance at 1.8 volts Quick Start Training

Quick Start Training

Appendix