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Operating System File Management, Exams of Social Sciences

United States International UniversitySocial Sciences

An overview of various aspects of file management in operating systems. It covers topics such as file structures, file operations, file protection, and network file access. The advantages and disadvantages of different file management approaches, including contiguous and non-contiguous file allocation, journaling file systems, and tree-structured directories. It also introduces concepts like file associations, logical and physical file views, and file access methods such as sequential and random access. System administration tasks related to file management, including user account management, file system backups, and system configuration. Additionally, it presents examples of system tools and utilities for file management in different operating systems like unix/linux and windows.

Typology: Exams

2023/2024

Available from 10/25/2024

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The Memory Hierarchy from More Costly to Less Costly (CPU) - Answers-System,
Online (Secondary), Tertiary, Off-Line
The Memory Hierarchy from Smaller to Larger (CPU) - Answers-Registers, Level 1
Cache, Level 2 Cache, Main Memory, Solid-State Disk, Fixed Rigid Disk, Optical Disks
(Jukeboxes), Magnetic Tapes (Robotic libraries), USB Flash Drives, Removable Hard
Drives
Current CPU Architecture Designs (CPU) - Answers-• Traditional modern architectures
• Complex Instruction Set Computers (CISC)
• Reduced Instruction Set Computers (RISC)
Current CPU Architecture (CPU) - Answers-• IBM Mainframe series
• Intel x86 family
• IBM POWER/PowerPC family
• ARM architecture
• Oracle SPARC family
• AMD
CISC (CPU) - Answers-- Equals a complex instruction set computers.
- Larger vocabulary and uses less steps to complete a task compared to RISC.
RISC (CPU) - Answers-- Equals a reduced instruction set computers
- Smaller vocabulary and uses fewer unique instructions to carry out tasks compared to
CISC.
PURDUE CNIT 176
FINAL EXAM
QUESTIONS AND
ANSWERS
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Download Operating System File Management and more Exams Social Sciences in PDF only on Docsity!

The Memory Hierarchy from More Costly to Less Costly (CPU) - Answers-System, Online (Secondary), Tertiary, Off-Line The Memory Hierarchy from Smaller to Larger (CPU) - Answers-Registers, Level 1 Cache, Level 2 Cache, Main Memory, Solid-State Disk, Fixed Rigid Disk, Optical Disks (Jukeboxes), Magnetic Tapes (Robotic libraries), USB Flash Drives, Removable Hard Drives Current CPU Architecture Designs (CPU) - Answers-• Traditional modern architectures

  • Complex Instruction Set Computers (CISC)
  • Reduced Instruction Set Computers (RISC) Current CPU Architecture (CPU) - Answers-• IBM Mainframe series
  • Intel x86 family
  • IBM POWER/PowerPC family
  • ARM architecture
  • Oracle SPARC family
  • AMD CISC (CPU) - Answers-- Equals a complex instruction set computers.
  • Larger vocabulary and uses less steps to complete a task compared to RISC. RISC (CPU) - Answers-- Equals a reduced instruction set computers
  • Smaller vocabulary and uses fewer unique instructions to carry out tasks compared to CISC.

PURDUE CNIT 176

FINAL EXAM

QUESTIONS AND

ANSWERS

Stored Program Computer (CPU) - Answers-• Modern day computers that store their programs in electronic memory

  • In contrast with historic computers that used wires or other means of entering program data
  • Two architectures support the stored program concept: The Von Neumann and the Harvard Architectures
  • A Plugboard is not a stored program computer. Von Neumann Architecture (CPU) - Answers-• It is named after the mathematician and early computer scientist John Von Neumann.
  • The computer has single storage system(memory) for storing data as well as program to be executed.
  • A single set of address/data buses between CPU and memory. Von Neumann Bottleneck (CPU) - Answers-• Processor can process an instruction faster than it can be transferred in from memory
  • So there is time while processor is waiting for transfer and is sitting idle
  • This is the Von Neumann Bottleneck Harvard Architecture (CPU) - Answers-• The name is originated from "Harvard Mark I" a relay based computer, which stored instruction on punched tape(24 bits wide) and data in electo-mechanical counters.
  • The computer has two separate memories for storing data and program.
  • Two sets of buses - one for data, one for instructions between CPU and memory. Problems with early CPU Architectures and solutions: (CPU) - Answers-• Large number of specialized instructions were rarely used but added hardware complexity and slowed down other instructions
  • Slow data memory accesses could be reduced by increasing the number of general purpose registers
  • Using general registers to hold addresses could reduce the number of addressing modes and simplify architecture design
  • Fixed-length, fixed-format instruction words would allow instructions to be fetched and decoded independently and in parallel Fetch-Execute Cycle Timing Issues (CPU) - Answers-• Computer clock is used for timing purposes for each step
  • Multiple operations are executed in parallel
  • Utilizes pipelining Superscalar Processing (CPU) - Answers-• Uses different execution resources (like ALU, or shift register)
  • Not separate cores or processors
  • Process more than one instruction per clock cycle
  • Separate fetch and execute cycles as much as possible
  • Buffers for fetch and decode phases
  • Parallel execution units
  • Utilizes pipelining Pipelined (CPU) - Answers-- Operations are broken down into sub-tasks
  • Different sub-tasks from different operations run in parallel Scalar Pipelined (CPU) - Answers-- Multiply the functional units
  • The same sub task from different operations run in parallel Superscalar Pipelined (CPU) - Answers-- Multiple the issue units
  • Multiple operations issued and completing simultaneously Pipeline Hazard (CPU) - Answers-• Control hazards (conditional branches - outcome of a branch is not known until after it is needed for next pipeline to use)
  • Data hazards - output of one operation is the input to a subsequent operation Control Hazards (CPU) - Answers-Outcome of a branch is not known until after it is needed for next pipeline to use Data Hazards (CPU) - Answers-Output of one operation is the input to a subsequent operation Pipeline Hazards' Solutions (CPU) - Answers-• Separate pipelines for both possibilities
  • Probabilistic approach
  • Requiring the following instruction to not be dependent on the branch
  • Instruction reordering (superscalar processing) Multiprocessing (CPU) - Answers-Reasons
  • Increase the processing power of a system
  • Parallel processing through threads: independent segments of a program that can be executed concurrently Multiprocessor system
  • Tightly coupled
  • Multicore processors—when CPUs are on a single integrated circuit
  • Multiprocessors - requires separate CPU sockets on same motherboard Multiprocessor Systems (CPU) - Answers-Identical access to programs, data, shared memory, I/O, etc. Easily extends multi-tasking and redundant program execution Two ways to configure
  • Hive-drone multiprocessing
  • Symmetrical multiprocessing (SMP) Hive-drone Multiprocessing (CPU) - Answers-Hive CPU
  • Manages the system
  • Controls all resources and scheduling
  • Assigns tasks to drone CPUs Advantages
  • Simplicity
  • Protection of system and data Disadvantages
  • Master CPU becomes a bottleneck
  • Reliability issues—if hive CPU fails, entire system fails Symmetrical Multiprocessing (CPU) - Answers-Each CPU has equal access to resources Each CPU determines what to run using a standard algorithm Disadvantages
  • Resource conflicts: memory, I/O, etc.
  • Complex implementation Advantages
  • High reliability
  • Fault tolerant support is straightforward
  • Balanced workload

the principle of locality tells us that once a byte is accessed, it is likely that a nearby data element will be needed soon. There are three forms of locality:

  • Temporal locality- Recently-accessed data elements tend to be accessed again.
  • Spatial locality - Accesses tend to cluster.
  • Sequential locality - Instructions tend to be accessed sequentially. Temporal Locality (CPU) - Answers-Recently-accessed data elements tend to be accessed again. Spatial Locality (CPU) - Answers-Accesses tend to cluster. Sequential Locality (CPU) - Answers-Instructions tend to be accessed sequentially. Flynn's Taxonomy (CPU) - Answers-Many attempts have been made to come up with a way to categorize computer architectures. Flynn's Taxonomy has been the most enduring of these, despite having some limitations. Flynn's Taxonomy takes into consideration the number of processors and the number of data paths incorporated into an architecture. A machine can have one or many processors that operate on one or many data streams. The four combinations of multiple processors and multiple data paths are described by Flynn as:
  • SISD: Single instruction stream, single data stream. These are classic uniprocessor systems.
  • SIMD: Single instruction stream, multiple data streams. Execute the same instruction on multiple data values, as in vector processors.
  • MIMD: Multiple instruction streams, multiple data streams. These are today's parallel architectures.
  • MISD: Multiple instruction streams, single data stream. Other examples of MIMD architectures are found in distributed computing, where processing takes place collaboratively among networked computers.
  • A network of workstations (NOW) uses otherwise idle systems to solve a problem.
  • A collection of workstations (COW) is a NOW where one workstation coordinates the actions of the others.
  • A dedicated cluster parallel computer (DCPC) is a group of workstations brought together to solve a specific problem.
  • A pile of PCs (POPC) is a cluster of (usually) heterogeneous systems that form a dedicated parallel system. SISD (CPU) - Answers-Single instruction stream, single data stream. These are classic uniprocessor systems. SIMD (CPU) - Answers-Single instruction stream, multiple data streams. Execute the same instruction on multiple data values, as in vector processors. MIMD (CPU) - Answers-Multiple instruction streams, multiple data streams. These are today's parallel architectures. Examples of MIMD architectures are found in distributed computing, where processing takes place collaboratively among networked computers.
  • A network of workstations (NOW) uses otherwise idle systems to solve a problem.
  • A collection of workstations (COW) is a NOW where one workstation coordinates the actions of the others.
  • A dedicated cluster parallel computer (DCPC) is a group of workstations brought together to solve a specific problem.
  • A pile of PCs (POPC) is a cluster of (usually) heterogeneous systems that form a dedicated parallel system MISD (CPU) - Answers-Multiple instruction streams, single data stream. NOW (CPU) - Answers-Network of Workstations (NOW) uses otherwise idle systems to solve a problem.
  • Communication with I/O controllers (see DMA) Example:
  1. CPU executes INPUT 24 instruction. Address 24 is copied to the I/O address register.
  2. Address 24 is recognized by the keyboard I/O controller. A read/write control line indicates that the instruction is an input.
  3. A buffer in the I/O controller holds a keystroke, in this case ASCII 68, the letter "D". The data is transferred to the I/O data register.
  4. From there it is copied to the appropriate accumulator or general-purpose register, completing the operation. Interrupt Driven I/O (I/O Technique) (I/O) - Answers-External input controls Direct Memory Access Controllers (I/O Technique) (I/O) - Answers-Method for transferring data between main memory and a device that bypasses the CPU Interrupts (I/O) - Answers-Signal that causes the CPU to alter its normal flow of instruction execution
  • Frees CPU from waiting for events
  • Provides control for external I/O initiation Examples
  • unexpected input
  • abnormal situation
  • illegal instructions
  • multitasking, multiprocessing Interrupt lines (hardware) (I/O) - Answers-One or more special control lines to the CPU Interrupt handlers (I/O) - Answers-• Program that services the interrupt
  • Also known as an interrupt routine or device driver Context (I/O) - Answers-• Saved registers of a program before control is transferred to the interrupt handler
  • Allows program to resume exactly where it left off when control returns to interrupted program Use of Interrupts (I/O) - Answers-Notify that an external event has occurred
  • Real-time or time-sensitive Signal completion
  • Printer ready or buffer full Allocate CPU time
  • Time sharing Indicate abnormal event (CPU originates for notification and recovery)
  • Illegal operation, hardware error

Software interrupts Servicing the Interrupt (I/O) - Answers-1. Lower priority interrupts are held until higher priority interrupts are complete

  1. Suspend program in progress
  2. Save context, including last instruction executed and data values in registers, in the PCB or the stack area in memory
  3. Branch to interrupt handler program
  4. Before interrupt arrives, program A is executing. The program counter points to the current instruction.
  5. When the interrupt is received by the CPU, the current instruction is completed, all the registers are saved in the stack area for in a special area known as a process control block. The PC is loaded with the starting location of a program B, the interrupt handler program. This causes a jump to program B, which becomes the executing program.
  6. When the interrupt routine is complete, the registers are restored, including the program counter, and the original program resumes exactly where it left off. Interrupt Processing Methods (I/O) - Answers-Vectored interrupt
  • Address of interrupting device is included in the interrupt
  • Requires additional hardware to implement Polling
  • Identifies interrupting device by polling each device
  • General interrupt is shared by all devices Vectored Interrupt (I/O) - Answers-• Address of interrupting device is included in the interrupt
  • Requires additional hardware to implement Polling (I/O) - Answers-• Identifies interrupting device by polling each device
  • General interrupt is shared by all devices Direct Memory Access (I/O) - Answers-Transferring large blocks of data Direct transfer to and from memory CPU not actively involved in transfer itself Required conditions for DMA
  • The I/O interface and memory must be connected
  • The I/O controller must be capable of reading and writing to memory
  • Conflicts between the CPU and the I/O controller must be avoided

storage

  • Relatively immune to physical shocks
  • Generates little heat or noise
  • Data is read/written in blocks
  • Wear-leveling used to extend life
  • Controller logic used to manage memory space and provide fast reads/writesSolid-state drives Magnetic Disks (Peripherals) - Answers-• Platter made of glass, metal, or plastic with a magnetic coating
  • Magnetic polarization used to determine 1s and 0s
  • Track - circle
  • Cylinder - same track on all platters
  • Block - small arc of a track
  • Sector - pie-shaped part of a platter
  • Head - reads data off the disk as disk rotates at high speed (10000+ RPM) Data Block Format
  • Interblock gap
  • Header
  • Data Formatting disk
  • Establishes the track positions, blocks, and headers needed before use of the disk Track (Peripherals) - Answers-Circle Cylinder (Peripherals) - Answers-Same track on all platters Block (Peripherals) - Answers-Small arc of a track Sector (Peripherals) - Answers-Pie-shaped part of a platter Head (Peripherals) - Answers-Reads data off the disk as disk rotates at high speed (10000+ RPM) Disk Layouts - CAV vs. CLV (Peripherals) - Answers-CAV - Constant Angular Velocity
  • Number of bits on each track is the same; denser towards the center
  • Spins the same speed for every track CLV - Constant Linear Velocity
  • All tracks have the same physical length and number of bits
  • Constant speed reading data off a track
  • Drive has to speed up when accessing close to the center of the drive and slow down when accessing towards the edge of the drive CAV (Peripherals) - Answers-Constant Angular Velocity
  • Number of bits on each track is the same; denser towards the center
  • Spins the same speed for every track CLV (Peripherals) - Answers-Constant Linear Velocity
  • All tracks have the same physical length and number of bits
  • Constant speed reading data off a track
  • Drive has to speed up when accessing close to the center of the drive and slow down when accessing towards the edge of the drive Disk Layout - Multiple Zone (Peripherals) - Answers-Multiple zone recording
  • Also known as zone bit recording (ZBR) or zone-CAV recording (Z-CAV)
  • Compromise between CAV and CLV
  • Disk divided into zones
  • Cylinders in different zones have a different number of sectors
  • Number of sectors in a particular zone is constant
  • Data is buffered so the data rate to the I/O interface is constant Locating a Block of Data (Peripherals) - Answers-Seek time: time required to move from one track to another Latency: time required for disk to rotate to beginning of correct sector Transfer time: time required to transfer a block of data to the disk controller buffer Seek Time (Peripherals) - Answers-Time required to move from one track to another Latency (Peripherals) - Answers-Time required for disk to rotate to beginning of correct sector Transfer Time (Peripherals) - Answers-Time required to transfer a block of data to the disk controller buffer Disk Access Times (Peripherals) - Answers-Average Seek time

Raid - Striped (Peripherals) - Answers-• A file segment is stored divided into blocks on different disks

  • Minimum of three drives needed because one disk drive is reserved for error checking
  • Writes - block of parity words from each block of data is created and put on the reserved error checking disk
  • Reads - parity data is used to check original data Raid Levels (Peripherals) - Answers-• RAID 0 - not true RAID; no error checking or redundancy, but data is placed across all drives for increased speed
  • RAID 1 - mirrored array
  • RAID 2, 3, 4 - arrays that are striped in different ways (deprecated)
  • RAID 5 - error checking blocks are spread across all drives
  • RAID 6 - double parity blocks, two drives per array can fail
  • RAID 10 - mix of performance of 0 with redundancy of 1 Used instead of 5 or 6 if performance is important Raid 0 (Peripherals) - Answers-Not true RAID; no error checking or redundancy, but data is placed across all drives for increased speed Raid 1 (Peripherals) - Answers-Mirrored array Raid 2, 3, 4 (Peripherals) - Answers-Arrays that are striped in different ways (deprecated) Raid 5 (Peripherals) - Answers-Error checking blocks are spread across all drives Raid 6 (Peripherals) - Answers-Double parity blocks, two drives per array can fail Raid 10 (Peripherals) - Answers-Mix of performance of 0 with redundancy of 1 Used instead of 5 or 6 if performance is

important Optical Storage (Peripherals) - Answers-Reflected light off a mirrored or pitted surface CD-ROM

  • 650 MB of data, approximately 550 MB after formatting and error checking
  • Spiral 3 miles long, containing 15 billion bits!
  • CLV - all blocks are same physical length
  • Block - 2352 bytes
  • 2k of data (2048 bytes)
  • 16 bytes for header (12 start, 4 id)
  • 288 bytes for advanced error control Laser strikes land: light reflected into detector Laser strikes a pit: light scattered Laser strikes land (Optical Storage) (Peripherals) - Answers-Light reflected into detector Laser strikes a pit (Optical Storage) (Peripherals) - Answers-Light scattered Types of Optical Storage (Peripherals) - Answers-Medium-powered laser blister technology also used for
  • CD-R, DVD-R, DVD-R, DVD+R
  • CD-RW, DVD-RW, DVD+RW, DVD-RAM, DVD+RAMBD-RE File compatibility issues between the different formats DVD - similar technology to CD-ROM
  • Shorter wavelength
  • Uses both sides of disc
  • Capacity up to 17GB Blu-Ray DVD - holds more than 50GB Magnetic Tape (Peripherals) - Answers-Offline storage Archival purposes Disaster recovery Tape cartridges
  • Linear tape open format
  • Currently store as much as 3TB of compressed data or 1.5TB of uncompressed data Displays (Peripherals) - Answers-Pixel - picture element Screen Size: diagonal length of screen Aspect ratio - X pixels to Y pixels
  • 4:3 - older displays
  • Inkjet - squirts heated droplets of ink
  • Laser printer Dots vs. pixels (Peripherals) - Answers-• 600 - 2400 dpi vs. 100 - 250 pixels per inch
  • Dots are on or off; pixels have intensities Laser Printer Operation (Peripherals) - Answers-1. Dots of laser light are beamed onto a drum
  1. Drum becomes electrically charged
  2. Drum passes through toner which then sticks to the electrically charged places
  3. Electrically charged paper is fed toward the drum
  4. Toner is transferred from the drum to the paper
  5. The fusing system heats and melts the toner onto the paper
  6. A corona wire resets the electrical charge on the drum User Input Devices (Peripherals) - Answers-• Keyboard, mouse, touch screens, graphics tablets, game controllers
  • Bar code and QR code readers
  • Magnetic Stripe Readers
  • RFID Input and Smart Cards
  • Voice Input
  • Optical Character Recognition Other Computer Peripherals (Peripherals) - Answers-Scanners
  • Flatbed, sheet-fed, hand-held
  • Light is reflected off the sheet of paper Multimedia Input
  • Digital Cameras, Audio Input Mobile Devices
  • Smartphones, tablets
  • Global Positioning Systems (GPS)
  • Linear accelerometers Network Communication Devices (Peripherals) - Answers-Network is just another I/O device Network I/O controller is the network interface card (NIC) Medium access control (MAC) protocols
  • Define the specific rules of communication for the network

Local Area Networks (LAN) (18 Networking) - Answers-• A network that connects computers and other supporting devices over a relatively small localized area

  • Typically ranging in size from a single room to multiple buildings in close range of each other
  • Most of the computers are personal computers or workstations
  • Routers and perhaps gateways are used to connect the LAN to other networks
  • Creating separate LANs for different departments or for different business functions is done to minimize extraneous traffic on the network
  • Most modern LANs are based on one of the Ethernet protocol standards Ethernet Hub (18 Networking) - Answers-• Based on bus topology
  • A passive central connection device used to simplify wiring and maintenance
  • Physical layer device where all of the connections are tied together inside the hub
  • Signals are broadcast to every device connected to the hub
  • Use of hubs is declining because switches generally provide better performance Ethernet Switches (18 Networking) - Answers-• Logically a star topology, not a bus topology
  • Able to set up a direction connection between any two nodes
  • Multiple pairs of nodes can communicate at the full bandwidth
  • Prevalent method for connecting wired local area networks Hub vs. Switch (18 Networking) - Answers-• When central node is Switch, logically add and physically a Star Topology
  • When central node is Hub, logically add and physically a Bus Topology Backbone Network (18 Networking) - Answers-Connects LAN's together Metropolitan Area Network (18 Networking) - Answers-A network larger in geographical scope than a LAN but within a range of less than 30 miles or 50 km Often there is a desire to create network links to connect locations that would require running wires through someone