Operating Systems - Midterm Exam 2 | CSE 430, Exams of Operating Systems

Material Type: Exam; Class: Operating Systems; Subject: Computer Science and Engineering; University: Arizona State University - Tempe; Term: Fall 2003;

Typology: Exams

Pre 2010

Uploaded on 09/02/2009

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CSE 430
FALL 2003 MIDTERM 2 NAME
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1. (23+3points extra credit) Process Coordination
As shown below, a counting semaphore can be implemented using a binary semaphore.
(a) (2) What range of values can a binary semaphore take on?
(b) (2) What range of values can a counting semaphore take on?
(c) (4) What is the reason for implementing a counting semaphore using a binary semaphore.
Note: Just saying binary semaphores are easier to implement gets you zero points. You have to
say why.
(d) (3) What is binary semaphore S1 used for?
(e) (3) What is binary semaphore S2 used for?
(f) (3) What does the signal(S2) at step 4 of the signal operation do?
(g) (3) What does the signal(S1) at step 6 of the signal operation do and when is it needed?
(h) (3) If C was > 0when a process performed the wait operation, what does the signal(S1) at step
7 of the wait operation do?
(i) (3points extra credit) If C was ≤ 0 when a process performed the wait operation, what does the
signal(S1) at step 7 of the wait operation do and why is it needed?
Data structures:
binary-semaphore S1, S2;
int C:
Initialization:
S1 = 1
S2 = 0
C = initial value of counting semaphore S
wait operation
1wait(S1);
2C--;
3if (C < 0) {
4signal(S1);
5wait(S2);
6}
7signal(S1);
signal operation
1wait(S1);
2C ++;
3if (C <= 0)
4signal(S2);
5else
6signal(S1);
pf3
pf4

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CSE 430

FALL 2003

MIDTERM 2

NAME

Put name on EVERY page

1. (23+3points extra credit) Process Coordination As shown below, a counting semaphore can be implemented using a binary semaphore. (a) (2) What range of values can a binary semaphore take on? (b) (2) What range of values can a counting semaphore take on? (c) (4) What is the reason for implementing a counting semaphore using a binary semaphore. Note: Just saying binary semaphores are easier to implement gets you zero points. You have to say why. (d) (3) What is binary semaphore S1 used for? (e) (3) What is binary semaphore S2 used for? (f) (3) What does the signal(S2) at step 4 of the signal operation do? (g) (3) What does the signal(S1) at step 6 of the signal operation do and when is it needed? (h) (3) If C was > 0when a process performed the wait operation, what does the signal(S1) at step 7 of the wait operation do? (i) (3points extra credit) If C was ≤ 0 when a process performed the wait operation, what does the signal(S1) at step 7 of the wait operation do and why is it needed? Data structures: binary-semaphore S1, S2; int C: Initialization: S1 = 1 S2 = 0 C = initial value of counting semaphore S wait operation 1 wait(S1); 2 C--; 3 if (C < 0) { 4 signal(S1); 5 wait(S2); 6 } 7 signal(S1); signal operation 1 wait(S1); 2 C ++; 3 if (C <= 0) 4 signal(S2); 5 else 6 signal(S1);

CSE 430 MIDTERM 2 FALL 2003 NAME

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2. (15) Deadlock For each of the two systems whose resource allocation state is shown by the graphs below, state whether the system is in deadlock or not. If the system is in deadlock, state what it is about the figure that indicates this, and if the system is not in deadlock give a possible completion sequence for the processes. System 1 System 2 3. (20) More Process Coordination (a) (10) The hardware test-and-set and swap instructions used to provide synchronization, implement memory access operations in a way that we could not assume when developing the software protocols for mutual exclusion. Because of this, software solutions to the critical section problem are unnecessary on a single machine. What is different about the characteristics of the memory operations assumed in the software protocols and the characteristics of the memory operations present in these test-and-set and swap instructions. NOTE : To answer this question you need to state the particular relevant characteristic of the memory operations assumed in the SW protocols and the particular relevant characteristic of the HW instructions. (b) (10) Explain why spinlocks are not appropriate for uniprocessor systems and are ok to use in multiprocessor systems.

CSE 430 MIDTERM 2 FALL 2003 NAME

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6. (16) Memory Management Assume search time is NOT an answer to (a) or (b) below. (a) (3) State an advantage inverted page tables have over ordinary page tables and why this is so. (b) (5) State an implementation problem that comes up in using inverted page tables that is much less of a problem when ordinary page tables are used. (c) (5) Why would one probably never use an inverted page table in the way shown in the figure below? You should assume there is a TLB associated with it that is not shown in the figure that handles most page translations and that on a miss a TLB entry is constructed and loaded into the TLB. What is usually added to this implementation to make it practical and what does it do? (d) (3) State a reason why ordinary hierarchical page tables are not suitable for use with 64-bit processors?