Other Data Path Designs: Microprogramed and Pipelined Datapaths | CS 231, Study notes of Computer Architecture and Organization

Material Type: Notes; Professor: Kale; Class: Computer Architecture I; Subject: Computer Science; University: University of Illinois - Urbana-Champaign; Term: Spring 2005;

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04/26/05 cs231Kale 1
Other DataPath designs:
Microprogrammed and pipelined datapaths
Laxmikant Kale
http://charm.cs.uiuc.edu
Parallel Programming Laboratory
Department of Computer Science
University of Illinois at Urbana Champaign
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Other DataPath designs:

Microprogrammed and pipelined datapaths

Laxmikant Kale

http://charm.cs.uiuc.edu

Parallel Programming Laboratory

Department of Computer Science

University of Illinois at Urbana Champaign

Problems with our datapath

  • (^) Other than the obvious: need

more registers, more bits in each

register (and therefore in

datapath)

  • The clock cycle time is

contrained by the longest

possible instruction execution

time.

  • Solution:
    • break an instruction execution into multiple cycles
    • Bucket brigade: pipelined datapath
    • Microprogrammed datapath Register write 3 ns MUX D 1 ns ALU or 4 ns Memory MUX B 1 ns Register read 3 ns Instruction 4 ns Memory Access PC 1 ns

Why multiple cycles?

  • Wouldn’t it be slower?
    • Not necessarily: if each clock cycle can be made shorter
    • Variable number of cycles for instructions (some 2, some 5)

New Datapath

  • Let us use one memory module
    • for both data and instructions
  • Allow for multiple cycles for each instruction

How to generate contol signals

  • Consequence of this datapath:
    • Needs a cycle to fetch instruction from memory
  • Control word:
    • the set of control signals
  • In our older datapath:
    • Control word was determined fully by the instruction
  • Here:
    • It depends on instruction and on which cycle within the instruction we are in
  • Example:

Generating control: sequential circuit

Control Unit IR: Instruction Register Cycle Counter Control word

Pipelined datapath

  • Simplified scenario:
    • 4 step assembly line
      • Instruction Fetch
      • Operand Fetch
      • Execution of operation
      • Writeback
    • Although total time for each instruction to finish is the same (or slightly larger)
    • The unit as a whole processes more instructions per unit time
    • Just as in assembly of a car
    • More on this in CS 232 and beyond