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Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
CURRENT MIRRORSINTRODUCTIONObjective The objective of this presentation is:1.) Introduce and characterize the current mirrors2.) Show how to improve the performance of the current mirrors3.) Demonstrate the design of current mirrors Outline • Simple MOS current mirrors• Simple BJT current mirrors• Cascode current mirrors• Wilson current mirrors• Regulated-cascode current mirrors• Summary
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
SIMPLE MOS CURRENT MIRRORS Characterization of Current Mirrors A current mirror is basically nothing more than a current amplifier. The ideal characteristics of a current amplifierare:• Output current linearly related to the input current,^ i^ =^ Ai^ out^ i^ in • Input resistance is zero• Output resistance is infinityIn addition, we have the characteristic^ V which applies not only to the output but also the input. MIN^ • V (in) is the range of input voltage over which the input resistance is not small MIN • V (out) is the range of the output voltage over which the output resistance is not large MIN Graphically: i^ in i i inout Slope+ += 1/ Rin Current v vinout Mirror-- i^ vin^ inV^ (in) MIN^
i^ i^ outout Slope = 1/ R^ out^ A^ i^1 v^ outV (out) MIN^^ Fig. 4.4-
Input Characteristics^ Transfer Characteristics^ Output Characteristics Therefore, we will focus on R , R , V (out),^ V (in), and^ A to characterize the current mirror. outinMINMINi^
Current Mirrors (5/11/00)^
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ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Influence of the Channel Modulation Parameter,
If the transistors are matched and the W/L ratios are equal, then^ i^ 1 +^ λ v^ ODS^2 = i 1 +^ λ v^ I^ DS^1 assuming that the channel modulation parameter is the same for both transistors (
L =^ L ).^1
Ratio error (%) versus drain voltage difference:8.0 7.0 6.0 5.0^ 4.0 3.0 2.0 1.0 0.00.^
λ^ =^ 0.02% Ratio Error v - v (volts) DS 2 DS (^1 100) × λ^ =^ 0.015 1 − (^12) DSDS v v λ^ =^ 0.01λλ + + (^11) Ratio Error v = 2.0 volt DS 1 5.01.0 2.03.0 4.0 v- v (volts)Fig. 4.4-3 DS 2 DS 1
Note that one could use this effect to measure^ λ. Measure^ V , V ,^ i^ and^ i^ and solve the above equation for the channel modulation parameter, DS^1 DS^2 I^ O^
Current Mirrors (5/11/00)^
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ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Influence of Mismatched Transistors Assume that^ v^ =^ v^ and that^ K ’^ ≠^ K ’ and^ VDS^1 DS^2
≠^ V. Therefore we have T 1 T^22 i K ’( v - V ) O 2 GS T 2 = 2 i K ’( v - V ) I 1 GS T 1
How do you analyze the mismatch? Use plus and minus worst case approach. Define∆ K’^ =^ K’ -^ K’K’^ = 0.5( K ’ +^ K^2 1
’ )^ ∆ V =^ V -^ V and^ V = 0.5( V + T^ T^2 T^1 T^ T^1
V ). T^2
∴^ K ’ =^ K’^ - 0.5^ ∆ K’^ K ’ =^ K’^ + 0.5^ ∆ K’^12
V =^ V -0.5^ ∆ V and^ V =^ V +0.5^ ∆ VT^1 T^ T^ T^2 T
T
Substituting these terms into the above equation gives,^2^ i^ ( K ’+0.5^ ∆ K’ )( v^ -^ V - 0.5^ ∆ V )^ OGS^ T^ T^ = =^2 i^ ( K ’-0.5^ ∆ K’ )( v^ -^ V + 0.5^ ∆ V )^ I^ GS^ T^ T
^2 ∆ V ∆ K’T 1 +^ 1 - 2 K’^ 2( v^ - V ) GST ^2 ∆ V ∆ K’T 1 -^ 1 + 2 K’^ 2( v^ - V ) GST
Assuming that the terms added to or subtracted from “1” are smaller than unity gives^2 ^ i^^ ∆ V O^ ∆ K’^ ∆ K’T ♠^ 1 +^ 1 +^ 1 - i^^2 K’^^2 K’^^ 2( v^ - V ) I^ GST ^
^2 ∆ VT 1 -Uses the approximation 1/(1+ε)^ ≈^ 1- 2( v - V ) GST
Retaining only first order products gives^ i^^2 ∆ V^ ∆ K’OT ♠^ 1 +-^ i^ K’^^ ( v^ - V ) I^ GST Assume^ ∆ K’/K’^ = ±5% and^ ∆ V /( v^ - V ) = ±10%. TGST ∴^ i^ / i^ ≈^ 1 ± 0.05 ±(-0.20) = 1 ± (0.25)^ ⇒^ OI^
±15% error in gain if tolerances are correlated.
Current Mirrors (5/11/00)^
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ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Influence of Error in Aspect Ratio of the Transistors Example 1 - Aspect Ratio Errors in Current MirrorsFigure 4.4-4 shows the layout of a one-to-four current amplifier. Assume that the lengths are identical (
L =^ L )^1
and find the ratio error if^ W =^5 ±^ 0.1^ μm. The actual widths of the two transistors are^1^ W =^5 ±^ 0.1^ μm and W =^20 ±^ 0.1^ μm^1 2 Solution We note that the tolerance is not multiplied by the nominal gain factor of 4. The ratio of
W to^ W and^2
consequently the gain of the current amplifier is0.11 ±^ i^ W^20 20 ± 0.10.1 O^2 =^ =^ =^4 ♠^4 1 ± i^ W 5 ± 0.1^ 0.1^20 I^^1 1 ±^5
±0.10.1±0.4 1 -♠^4 1 ± - = 4 - (±0.06) 5 20 20
where we have assumed that the variations would both have the same sign (correlated). It is seen that this ratioerror is 1.5% of the desired current ratio or gain.
i^ iIO^ M1^ M2++ V VDS2DS^1 + VGS - --
i^ iO^ I^ M1M2^ GND Fig. 4.4-
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Influence of Error in Aspect Ratio of the Transistors-Continued Example 2 - Reduction of the Aspect Ratio Errors in Current MirrorsUse the layout technique illustrated in Fig. 4.4-5 and calculate the ratio error of a current amplifier having thespecifications of the previous example. Solutions The actual widths of M1 and M2 are^ W =^5 ±^ 0.1^ μm and^ W =^ 4(5^ ±^ 0.1)^ μm^1 2 The ratio of^ W to^ W and consequently the current gain is given below and is for all practical purposes^2 1 independent of layout error.^ i^ 4(5 ± 0.1) O =^ =^4 i^ 5 ± 0.1^ I^ ^ ^ ^
i^ iIO^ i M1M2bM2a M2dM2c^ iIO ^ M1^ M2 GND GND^ Fig. 4.4-6^ ^
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
SIMPLE BJT CURRENT MIRRORS Characterization of a Simple BJT Current Mirror^ i^ iC =^ i^12 2^ iC^1^ iBiB^1 2 Q1^ Q2+^ v^ BE -^ CM10 VA 2 R = r = out o 2 I C 2 V 1 t R ≈ = in g I m 1 C 1 V (out) = v (sat) ≈ 0.2V MINCE V (in) = V ≈ 0.6 to 0.7V MINBE and I s 2 A = if the transistors are matched and^ β^ =^ ∞. i I s 1
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Page 11 ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Simple BJT Current Mirror Matching Circuit:^ i^1
i^ C^1 = i + i + i = i + i = +^ i^ C 1 B 1 B 2 E 1 B 2 B^2 α F^1 v CE 1 i = 1 + I exp( v / V ) C 1 s 1 BEt VA 1 and v CE 2 i = i = 1 + I exp( v / V ) C 2 2 s 2 BEt VA 2
Now, v^ I^ CE^1 s^1 ^ i =^ 1 +^ exp( v^ / V ) +^ i^^1 BEtB^2 ^ V^ α A^1 F^1
i i 1-^ α vC 22 F^22 and i = = = 1+^ I^ exp( v^ B 2 s^2 BE ^ V β β^ α A^2 F 2 F 2 F^2
/ V ) t
vI^ 1-^ α v ^1 s^1 F^22 ∴ i = 1 +^ +^ 1+^ I^ 1 s^2 ^ V^ V^ α^ α A^1 A^2 F^1 F^2
exp( v^ / V ) BEt
i^ i^ =^ i^1 C^2 2 i C^1 +^ i^ iBB^1 2 +Q1^ Q2 vCE =^ v^2 2 + v = vCE 1 1^ v - BE - -^ CM11 Finally, v^2 ^ 1+^ ^ V iA^22 = i v I^ 1-^ α v 1 1 s^1 F^22 1 +^ +^ 1+^ I^ s^2 ^ V^ V^ α^ α A^1 A^2 F^1 F^2
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Page 13 ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Geometrical Influence on BJT Matching^ If everything is ideal (^ β=^ ∞^ and^ V =^ VF^ CE^1
), the CE 2
matching of the currents is determined by the matching of thesaturation currents,^ I^ , which is given as s^22 qn^ D qn^ D inin^ I^ =^ A =^ As^ E^ ENW ( V )^ Q ( V )^ ABCBBCB Therefore, the transistor matching directly depends on how wellthe emitter areas are matched.If a current gain greater than 1 is required, the emitter areas should be implemented as follows:^ CM
C1 C2 E2E1 B2 B
Metal 2Metal 1 Current gain of the above structure is 1.5.
Emitter AreaCollectorContact BaseContact CM18Emitter Contact
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
† Rules for Matching of NPN BJT Transistors 1. Use identical emitter geometries.2. The emitter diameter should equal 2-10 times the minimum allowed diameter.3. Maximize the emitter area-to-periphery ratio (circle the best, square okay).4. Place matched transistors in close proximity5. Keep the layout of matched transistors as compact as possible.6. Construct ratioed pairs and quads using even integer ratios between 4:1 and 16:17. Place matched transistors far away from power devices.8. Place matched transistor in low-stress areas (thermal and physical).9. Place moderately or precisely matched transistors on axes of symmetry of the die.10. Do not allow the buried layer shadow to intersect matched emitters (must overlay the emitter area).11. Place emitters far enough apart to avoid interactions.12. Increase the base overlap of moderately or precisely matched emitters.13. Operate matched transistors on the flat portion of the beta curve.14. The contact geometry should match the emitter geometry (circular contact for circular structure, square contactfor square structure, etc.).15. Consider using emitter degeneration.† Alan Hastings, “The Art of Analog Layout”, Chapter 9, 1998 (Unpublished text, [email protected])
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Simple BJT Current Mirror for Finite^ ββββ Circuit:If the transistors are matched and
v^ =^ v^ , then^ i^ =^ i^ but CE^1 CE^2 C^1 C^2 2 i = i - 2 i = i 1 1+ C 1 1 B β i 21 ∴ A = = i i 21 1+ β
If^ βis small then appreciable error is introduced into the current gain. F^ Solutions to this problem:^ V^ CC
CM V^ CC i i (^) C 1 C (^1) i C (^2) Q3 Q1 Q2 Q1 Q
i^ C^2 Q3or
i^ i =^ i^1 C^2 2 i C^1^ iBi^1 B^2 Q1^ Q2+^ v^ BE -^ CM
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Base-Current Cancellation In a BiCMOS process, base current cancellation is possible and using the following technique.
VDD M2M1 M3 M4^ I^ B^2 Q2 I B 2^ I^ I ≈ 0 B^1 Q1^ CM
If Q1 and Q2 are matched, then^ I^ ≈^ I^ and^ I^ C^1 C^2 B^1
≈^ I^. B^2
The cascode current mirror is used to make sure that
I^ =^ I^. B^1 B^2
Current Mirrors (5/11/00)^ ECE 4430 - Analog Integrated Circuits and Systems^
^ P.E. Allen, 2000
Large Output Swing Cascode Current Mirror
VDD I^ I REF^ i^ REF O^ i^ I D5=G3^ M2M4+^ M5^ 1/1 rds^5 1/41/1^ gmv^^5 gs^5^ viniin M1M3+D3=S51/11/1^ gmv^^3 gs^3 r^ vds^1 s^5 gmvin^3 =^ - S3=G5- Fig. 4.4-
-^ R ≈^ g^ r^ r^ out^ m2^ ds^2 ds^1 •^ R =?^ v^ =^ r^ ( i^ -^ g^ v^ ) +^ v^ =^ r^ ( in^ in^ ds^5 in^ m^5 gs^5 s^5 ds^5
i^ g^ v^ ) +^ v^ =^ r^ i^ + (1+ g^ r^ ) v^ in^ +^ m^5 s^5 s^5 ds^5 in^ m^5 ds^5 s^5 But, v = r ( i - g v ) s 5 ds 3 in m 3 in ∴ v = r i + (1+ g r ) r i - g r^ (1+ g^ r^ ) v^ in ds 5 in m 5 ds 5 ds 3 in m^3 ds^3 m^5 ds^5 in v r + r + r g r inds 5 ds 3 ds 3 m 5 ds 51 R = = ♠^ in i g r (1+ g r )^ g^ in m 3 ds 3 m 5 ds 5 m^3
-^ V (out) = 2 VMINON •^ V (in) =^ V +^ VMINT^ ON •^ Current gain is excellent because^ v^ =^ v^. DS^1 DS^3
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^ P.E. Allen, 2000
Self-Biased Cascode Current Mirror^ V^ V^ DD^ DDII^1 2 i^ i^ outin^ R M3^ M4 M2^ M^
+^ R^ gmv^3 gs^3 + +^ r^ vds^3 in +^ vvin^2 vg^ vr^^1 m^1 gs^1 ds^1 - - - -^ Small-signal model to calculate^ R^. in Self-biased, cascode current mirror^ i^ in Fig. 4.4-
-^ R =?^ v^ =^ i^ R^ +^ r^ ( i^ - g^ v^ ) +^ r^ ( iin^ in^ inds^3 inm^3 gs^3 ds^1
- g^ v^ ) inm^1 gs^1 But, v = v - i R and v = v - r^ ( i^ - g^ v^ ) =^ v^ -^ r^ i^ +^ g^ r^ ( v^ - i^ Rgs 1 in ings 3 in ds^1 inm^1 gs^1 in^ ds^1 in^ m^1 ds^1 inin
∴^ v^ =^ i^ R^ +^ r^ i^ -^ g^ r^ [ v^ -^ r^ i^ +^ in^ inds^3 in^ m^3 ds^3 in^ ds^1 in^
g^ r^ ( v^ - i^ R )] +^ r^ [ i^ -^ g^ ( v^ + i^ R )] m^1 ds^1 ininds^1 in^ m^1 inin
v^ [1 +^ g^ r^ +^ g^ r^ g^ r^ +^ g^ r^ ] =^ iinm^3 ds^3 m^1 ds^1 m^3 ds^3 m^1 ds^1 in
[ R^ +^ r^ +^ r^ +^ g^ r^ r^ +^ g^ r^ g^ r^ Rds^1 ds^3 m^3 ds^3 ds^1 m^1 ds^1 m^3 ds^3
]
R^ +^ r^ +^ r^ +^ g^ r^ r^ +^ g^ r^ g^ ds^1 ds^3 m^3 ds^3 ds^1 m^1 ds^1 m^3 R = in
r^ Rds^31 ♠^ +^ R 1 + g r + g r g r + g r g^ m 3 ds 3 m 1 ds 1 m 3 ds 3 m 1 ds^1 m^1
-^ R ≈^ g^ r^ r^ out^ m^4 ds^4 ds^2 •^ V (in) =^ V + 2 V • V (out) = 2 VMINT^ ON^ MINON -^ Current gain matching is excellent
