Download Memory Management in Operating Systems: An In-depth Study and more Lecture notes Computer Aided Design (CAD) in PDF only on Docsity!
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Chapter 9: Memory Management
Background
Swapping
Contiguous Allocation
Paging
Segmentation
Segmentation with Paging
Background
Program must be brought into memory and placed within
a process for it to be run.
Input queue – collection of processes on the disk that are
waiting to be brought into memory to run the program.
User programs go through several steps before being
run.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Binding of Instructions and Data to Memory
Compile time : If memory location known a priori,
absolute code can be generated; must recompile code if
starting location changes.
Load time : Must generate relocatable code if memory
location is not known at compile time.
Execution time : Binding delayed until run time if the
process can be moved during its execution from one
memory segment to another. Need hardware support for
address maps (e.g., base and limit registers ).
Address binding of instructions and data to memory addresses can
happen at three different stages.
Multistep Processing of a User Program
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Dynamic relocation using a relocation register
Dynamic Loading
Routine is not loaded until it is called
Better memory-space utilization; unused routine is never
loaded.
Useful when large amounts of code are needed to handle
infrequently occurring cases.
No special support from the operating system is required
implemented through program design.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Dynamic Linking
Linking postponed until execution time.
Small piece of code, stub , used to locate the appropriate
memory-resident library routine.
Stub replaces itself with the address of the routine, and
executes the routine.
Operating system needed to check if routine is in
processes’ memory address.
Dynamic linking is particularly useful for libraries.
Overlays
Keep in memory only those instructions and data that are
needed at any given time.
Needed when process is larger than amount of memory
allocated to it.
Implemented by user, no special support needed from
operating system, programming design of overlay
structure is complex
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Schematic View of Swapping
Contiguous Allocation
Main memory usually into two partitions:
✦ Resident operating system, usually held in low memory with
interrupt vector.
✦ User processes then held in high memory.
Single-partition allocation
✦ Relocation-register scheme used to protect user processes
from each other, and from changing operating-system code
and data.
✦ Relocation register contains value of smallest physical
address; limit register contains range of logical addresses –
each logical address must be less than the limit register.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Hardware Support for Relocation and Limit Registers
Contiguous Allocation (Cont.)
Multiple-partition allocation
✦ Hole – block of available memory; holes of various size are
scattered throughout memory.
✦ When a process arrives, it is allocated memory from a hole
large enough to accommodate it.
✦ Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
process 9
process 10
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Paging
Logical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available.
Divide physical memory into fixed-sized blocks called frames
(size is power of 2, between 512 bytes and 8192 bytes).
Divide logical memory into blocks of same size called pages.
Keep track of all free frames.
To run a program of size n pages, need to find n free frames
and load program.
Set up a page table to translate logical to physical addresses.
Internal fragmentation.
Address Translation Scheme
Address generated by CPU is divided into:
✦ Page number (p) – used as an index into a page table which
contains base address of each page in physical memory.
✦ Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Address Translation Architecture
Paging Example
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Implementation of Page Table
Page table is kept in main memory.
Page-table base register ( PTBR) points to the page table.
Page-table length register (PRLR) indicates size of the
page table.
In this scheme every data/instruction access requires two
memory accesses. One for the page table and one for
the data/instruction.
The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers
(TLBs)
Associative Memory
Associative memory – parallel search
Address translation (A´, A´´)
✦ If A´ is in associative register, get frame # out.
✦ Otherwise get frame # from page table in memory
Page # Frame
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Paging Hardware With TLB
Effective Access Time
Associative Lookup = ε time unit
Assume memory cycle time is 1 microsecond
Hit ratio – percentage of times that a page number is
found in the associative registers; ration related to
number of associative registers.
Hit ratio = α
Effective Access Time (EAT)
EAT = (1 + ε) α + (2 + ε)(1 – α)
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Page Table Structure
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
Hierarchical Page Tables
Break up the logical address space into multiple page
tables.
A simple technique is a two-level page table.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is
divided into:
✦ a page number consisting of 20 bits.
✦ a page offset consisting of 12 bits.
Since the page table is paged, the page number is further
divided into:
✦ a 10-bit page number.
✦ a 10-bit page offset.
Thus, a logical address is as follows:
where p
i
is an index into the outer page table, and p
is the
displacement within the page of the outer page table.
page number page offset
p
i
p
d
Two-Level Page-Table Scheme
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Hashed Page Table
Inverted Page Table
One entry for each real page of memory.
Entry consists of the virtual address of the page stored in
that real memory location, with information about the
process that owns that page.
Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs.
Use hash table to limit the search to one — or at most a
few — page-table entries.
Silberschatz, Galvin and Gagne 2002
Operating System Concepts
Inverted Page Table Architecture
Shared Pages
Shared code
✦ One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
✦ Shared code must appear in same location in the logical
address space of all processes.
Private code and data
✦ Each process keeps a separate copy of the code and data.
✦ The pages for the private code and data can appear
anywhere in the logical address space.
