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A part of the lecture notes from ece 440: electronic devices i course at the university of illinois at urbana-champaign, delivered by prof. Eric pop. The lecture focuses on the electrostatics of p-n diodes, discussing the depletion region, space charge region, and quasi-neutral regions. The professor explains the concept of the built-in potential and its calculation using the poisson equation and fermi level alignment.
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P-N Diode Electrostatics Last time, we talked about p-n junction built-in voltage V 0. Today: more about p-n electrostatics. In the middle, where there are huge p-to-n concentration gradients, what happens?
What is left in the middle after the electrons and holes there are gone? Note: we will keep making the depletion approximation which means an ___________________________ between the space charge (ND – NA) region and the two quasi-neutral (n and p) regions. What is the depletion region? What is the space charge region (SCR)? What are the quasi-neutral regions (QNR)? If the SCR is W = xp + xn in width, do the two (xp, xn) sides have to be equal? Why/why not? What’s the total charge on either side of the junction? On the p-side: On the n-side: OK, let’s calculate the depletion widths now.
This isn’t too hard with the Poisson equation (Gauss’ Law). Recall: q E ^2 V In one dimension, in the depletion region, this is just: On the p-side: On the n-side: Integrate over the space charge density on either side, and obtain the maximum field at the junction: E 0 The field distribution is triangular, because the charge distribution is rectangular ( depletion approximation ).
Now, the built-in potential is easy to calculate. The voltage potential across the junction is just (minus) the integral over the electric field: So the built-in voltage V 0 is the area under the electric field triangle.
What if I vary the externally applied voltage? Remember, a positive outside voltage “grabs” the Fermi level on the side it’s applied on and drags it down. (negative pulls it up). How do we remember this? Think of the simple resistor band diagram, which way the electric field points (external + to -) and which way the electrons “slide down” or holes “bubble up.” A forward bias is + applied to the p-side, which lowers the built-in voltage barrier (V 0 – Vfwd) where Vfwd > 0. A reverse bias is – applied to the p-side, which increases the built-in voltage barrier (V 0 – Vrev) where Vrev < 0. [if we’re out of time, use this space to draw the band diagrams, if you need a hint look up Fig. 5-13 in the book]
Example: An abrupt silicon p-n junction has p-side NA = 10 16 cm
