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Operating Systems Lecture No.
Operating Systems
Lecture No. 36
Reading Material
Chapter 9 of the textbook Lecture 36 on Virtual TV
Summary
Paged segmentation Examples of paged segmentation: MULTICS under GE 345 and OS/2, Windows, and Linux under Intel CPUs
Paged Segmentation
In paged segmentation, we divide every segment in a process into fixed size pages. We need to maintain a page table per segment CPU’s memory management unit must support both segmentation and paging. The following snapshots illustrate these points.
Paged Segmentation
1
3
2
4
logical memory
5
physical memory
1
3
2
4
logical memory
5
physical memory
1
2
0
3
0 1 2 3...
10
126 127
3 1 126 10 page table
The logical address is still <s,d>, with s used to index the segment table. Each segment table entry consist of the tuple
<segment-length, page-table-base>
The logical address is legal if d < segment-length. The segment offset, d, is partitioned into two parts: p and d’, where p is used to index the page table associated with the segment s and d’ is used as offset within the page p. p indexes the page table to retrieve frame, f, and physical address (f,d’) is formed. The following diagrams show the format of logical address and its division, and the hardware support needed for logical to physical address translation.
a) Logical address and its partition
b) Hardware support needed for logical to physical address translation
MULTICS Example
We now take the example of one of the finest operating systems of late 1960s and early 1970s, known as the MULTICS operating system. Here are the specifications of the CPU supported by MULTICS and calculation of its various parameters such as the largest segment size supported by MULTICS.
GE 345 processor Logical address = 34 bits
s d
p (^) d’
index segment table index page table
offset within the
page p
Intel 80386 Example
IBM OS/2, Microsoft Windows, and Linux run on it Paged segmentation with two-level paging Logical address = 48 bits 16-bit selector and 32-bit offset Page size = 4 KB 4-byte page table entry 32-entry TLB, covering 32*4K (128 KB) memory … TLB Reach
15 3921
3 849
3921
12 12 849
13137
Logical/virtual address and its division for Intel 80386 and higher
Real Mode
20-bit physical address is obtained by shifting left the Selector value by four bits and adding to it the 16-bit effective address.
13-bit Segment #
16-bit Selector
g p
32-bit Offset
s (^) 2-bit field for specifying the privilege level
1-bit field to specify GDT or LDT
