Pipe lining : Pipeline Hazard presentation, Slides of Advanced Computer Architecture

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Pipeline Hazards

Advance Computer Architecture Nora Almotery

OUTLINES

Pipeline Hazards Types Of Pipeline Hazards. Structural Hazards. Data Hazards. Control Hazards.

Classes of Hazards

Arise from resource conflicts. HW cannot support all possible combinations of instructions Arise when an instruction depends on the results of a previous instruction Result from branch, other instructions that change flow of Program. Structural Hazards (^) Data Hazards Control Hazards

Structural Hazard

It can be generated by:

1. Functional unit is not fully pipelined.
2. Resources that are shared between pipe stages. If certain combination of instructions can’t be accommodated because of resource conflicts, the machine is said to have a structural hazard Consider the architecture in Fig1( same memory for instructions and data ) Fig 1

Structural Hazard

Why a designer allows structural hazard? To reduce cost (^) To reduce latency A machine with structural hazard will have lower CPI. realistic solution? Answer: Add more hardware.

Data Hazard

Consider the execution of following instructions, on our pipelined example processor: ADD R1, R2, R SUB R4, R1, R AND R6, R1, R OR R8, R1, R XOR R10, R1, R Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on an un-pipelined machine

Types Of Data Hazards

• WAR (write after read)
• WAW (write after write) • RAR (read after read)
• RAW (read after write)

Solving Data Hazard

by a simple hardware technique called forwarding (also called bypassing or short-circuiting ) Unfortunately not all data hazards can be handled by forwarding. Consider the following sequence: LW R1, 0(R2) SUB R4, R1, R AND R6, R1, R OR R8, R1, R

• Before stall insertion
• After stall insertion

Branch / Control Hazards

When a branch is executed it may or it may not change the PC (to other value than its value + 4) Can cause a greater performance loss than the data hazards ▪ If a branch is changing the PC to its target address, then it is a taken branch ▪ If a branch doesn’t change the PC to its target address, then it is a not taken branch

Dealing W/Branch Hazards: Always Stall

Branch taken

• Wait 3 cycles
• No proper instructions in the pipeline
• Same delay as without stalls (no time lost) Branch not taken - Still must wait 3 cycles - Time lost - Could have spent CCs fetching, decoding next instructions

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