Pipelines - High Performance Computing - Lecture Slides, Slides of Computer Science

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High Performance Computing

Lecture 22

2

Pipelines

 Used for transportation of liquids or gases

over long distances

 1000s of kms

 Built with periodic pump/compressor stations to

keep the fluid flowing

1000 kms refinery (^) city

4

Processor Pipelining

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

• Execution time of each instruction is still 5 cycles, but the throughput is now 1 instruction per cycle
• Initial pipeline fill time (4 cycles), after which 1 instruction completes every cycle time i i i i

clock cycles

5

MIPS 1 Instructions: 3, 4 or 5 cycles

IF ID EX MEM WB

time IF ID EX MEM WB

LW R1, 0(R2)

ADD R3, R1, R

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Pipelined Processor Datapath

Mem

PC Reg File Sign extend IF ID 4 ALU Zero? Mem EX MEM^ WB

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Some Terminology

 Pipeline stages: IF, ID, EX, MEM, WB

 We describe this as a 5 stage pipeline

 or a pipeline of depth 5

 Assume that the time delay through each

stage is the same (say 1 clock cycle)

 Pipeline Speedup =

IF ID EX MEM WB

pipelined non pipelined

time

time



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 A pipeline with p stages could give a speedup

of p (compared to a non-pipelined processor

that takes p cycles for each instruction)

 i.e., A program would run p times faster on

the pipelined processor (than on the non-

pipelined processor)

 if on every clock cycle, an instruction completes

execution

Pipeline Speedup

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Problem: Pipeline Hazards

A situation where an instruction cannot

proceed through the pipeline as it should

Hazard: a dangerous (hazardous) situation

From the perspective of correct program

execution

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Problem: Pipeline Hazards

A situation where an instruction cannot

proceed through the pipeline as it should

1. Structural hazard: When 2 or more

instructions in the pipeline need to use the

same resource at the same time

2. Data hazard: When an instruction depends

on the data result of a prior instruction that

is still in the pipeline

3. Control hazard: A hazard that arises due to

control transfer instructions

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Structural Hazard

MEM and IF use memory at same time i IF ID EX MEM WB LW R3, 8(R2) i + 1^ IF^ ID EX MEM WB i + 2 IF ID EX MEM WB i + 3 IF

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Petroleum pipeline analogy?

refinery (^) city Kerosene Diesel Air

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Structural Hazard

B B B B

MEM and IF use memory at same time i IF ID EX MEM WB LW R3, 8(R2) i + 1^ IF^ ID EX MEM WB i + 2 IF ID EX MEM WB i + 3 IF i + 3 IF ID EX MEM WB

B

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Problem: Pipeline Hazards

A situation where an instruction cannot

proceed through the pipeline as it should

1. Structural hazard: When 2 or more

instructions in the pipeline need to use the

same resource at the same time

2. Data hazard: When an instruction depends

on the data result of a prior instruction that

is still in the pipeline

3. Control hazard: A hazard that arises due to

control transfer instructions

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Data Hazard

i IF ID EX MEM WB add R3 , R1, R i + 1 (^) IF IDB^ EXB^ MEMB WBB sub R4 , R3, R ID EX MEM WB ID EX MEM WB

B B B B

R3 updated by instruction i R3 read by instruction i+ time 1 2 3 4 5 Idea: Delay (or stall) the progress of instruction i+ through the pipeline until the data is available in register R