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Various pipelining techniques to enhance processor performance. Topics include superpipelining (deep pipelining) with longer pipelines, multiple issue with static and dynamic functional units, and dynamic scheduling to avoid pipeline hazards. The document also covers the mips superscaler architecture and its implementation, as well as code scheduling and loop unrolling techniques to optimize pipelining.
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ALU or branch instruction IF ID EX MEM WB Load or store instruction ALU or branch instruction Load or store instruction ALU or branch instruction Load or store instruction ALU or branch instruction Load or store instruction
IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB
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Loop: lw $t0, 0($s1) 1 addi $s1, $s1, -4 2 addu $t0, $t0, $s2 3 bne $s1, $zero, Loop sw $t0, 0($s1) 4
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Loop: addi $s1, $s1, -16 lw $t0, 0($s1) 1 lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw $t0, 0($s1) 5 addu $t3, $t3, $s2 sw $t1, 12($s1) 6 sw $t2, 8($s1) 7 bne $s1, $zero, Loop sw $t3, 4($s1) 8
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Loop: lw $t0, 0($s1) # $t0 = array element add $t0, $t0, $s2 # add scalar in $s sw $t0, 0($s1) # store result addi $s1, $s1, -4 # decrement pointer bne $s1, $zero, Loop
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Loop: lw $t0, 0($s1) lw $t1, -4($s1) add $t0, $t0, $s add $t1, $t1, $s sw $t0, 0($s1) sw $t1, -4($s1) addi $s1, $s1, - bne $s1, $zero, Loop
data hazards are gone
