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Power Dissipation
Chip power dissipation budget:
air cooled packages (cheap) < 10W/chip
heat sinks < 200W/chip
cooling fluid (expensive) < 1000W/chip
Static Power Dissipation
CMOS logic gates became popular in the early 1980’s because of low power consumption.
I DC ≈ 0 ⇒P DC ≈ 0
The power is not quite zero because of leakage currents. As device sizes have decreased, leakage currents have come to be a significant part of overall power dissipation.
There is small power dissipation from diffusion layer leakage currents, I (^) leak 1 μA cm 2 < ⁄ ,
through parasitic reversed bias p-n junction diodes. Fig. 2.19 p. 90.
In modern processes with small VT, the leakage current through “off” transistors has
become much more important. We have assumed that when VGS < VT that there is no
drain current, but there is non-zero subthreshold current that increases exponentially as VT
is lowered (see eq. 2.34, p. 88). Many modern processes offer a high VT transistor (high
VT => low ID => slow) to save power in non-critical delay paths.
As process dimensions continue to shrink, quantum mechanical tunneling of electrons through the thin oxide underneath the gate produces significant current. Fig. 2.20, p. 90.
Pseudo nMOS
I (^) on
V (^) dd R (^) on p +R (^) on n
pFETs always on
on off
off on
or two possible states for nFETs
On average, 1/2 of nFETs are on at any given time.
=> P DC
---V (^) dd ⋅ I (^) on^1 2
V (^) dd 2
R (^) on p +R (^) on n
for each gate and the total static power dissipation is
P (^) DC N (^) gates^1 2
V (^) dd 2
R (^) on p +R (^) on n
where Ngates is the number of pseudo NMOS gates. Typical values are 0.1- 1.0 mW/gate.
Dynamic Power
There are two components to the switching transient current:
- load capacitor charge/discharge through one FET
- short circuit between power/ground through both FET’s
I (^) Dp C (^) load dt
dV (^) out = –
V (^) DSp = –(V (^) dd – V (^) out)
I (^) Dn C (^) load dt
dV (^) out = –
V (^) DSn = V (^) out
Therefore
P (^) d
T (^) sw
-------- (^) C (^) load dt
dV (^) out (V (^) dd – V (^) out) dt 0
T (^) sw ⁄ 2
T (^) sw
-------- (^) C (^) load dt
dV (^) out
- V (^) out dt T (^) sw ⁄ 2
T (^) sw
These integrals over time can be converted to integrals over voltage as in the following
dt
dV (^) out dt t 1
t 2
∫ V …^ dV^ out
out (t^1 )
V (^) out (t 2 )
P (^) d^1 T (^) sw
-------- (^) C (^) load ( V (^) dd – V (^) out) dV (^) out 0
V (^) dd
T (^) sw
-------- – C (^) load V (^) outdV (^) out V (^) dd
0
C (^) load T (^) sw
V (^) dd 2
2
V (^) dd 2
2
Tsw is the switching period (can be different for every gate!)
Define fsw = 1/Tsw as switching frequency (can be different for every gate!)
Define activity factor α = fsw/f where f is the clock frequency. Usually α < 1, but can be
larger than 1 when glitches occur.
P (^) d αC (^) load V (^) dd 2 = f
total cap. with chang- ing voltage
voltage swing
switching frequency
activity factor
Note: Power consumption reduced by reducing
- Vdd^2 => reduce voltage swing (reduce power supply)
- Cload (not capacitance on power/ground lines) => rearrange circuit topology to reduce load capacitance
- f => reduce frequency (reduce clock rate)
- α => reduce activity factor (turn clocks off during idle mode)
The dynamic power dissipation is the dominant mode of power dissipation in full comple- mentary CMOS circuits. Every logic family has dynamic power dissipation, but it is usu- ally not the dominant mode for gates with DC power dissipation. Let’s compare CMOS with pseudo NMOS.
f
P
PDC
NMOS
CMOS
The load capacitance for NMOS is smaller than CMOS which makes the dynamic power consumption for NMOS smaller than CMOS, but the DC power consumption of CMOS is orders of magnitude smaller than NMOS. Total CMOS power dissipation is smaller when
P (^) d (CMOS ) <P (^) DC (NMOS ) +P (^) d (NMOS )
C (^) load (CMOS )V (^) dd 2 f
V (^) dd 2
R (^) on p +R (^) on n
< ----------------------------^ +C (^) load (NMOS )V (^) dd^2 f
f 1 2
( R (^) on p +R (^) on n) ( C (^) load (CMOS ) – C (^) load (NMOS ))
f
t (^) r +t (^) f
T >t (^) r +t (^) f
As long as the switching period is larger than the sum of the rise and fall times, CMOS cir- cuits have a power dissipation advantage. In clocked systems, the switching period is close to the clock period which is usually about 10 times typical gate rise and fall times. This allows CMOS gates to dissipate about 10 times less average power than pseudo NMOS.
CMOS Short Circuit Power Dissipation
We have been assuming up to this point that the input signals change so fast that the nFETs are never on at the same time the pFETs are on. For more slowly changing inputs, this is not the case. There will be a path from power to ground through the partially turned on FETs for a short time for any input waveform with a finite rise/fall time. Let’s assume
I (^) Dp
βp 2
E (^) satp L (^) p ( V (^) in ( )t – V (^) dd–V (^) Tp) 2
V (^) in ( )t – V (^) dd– V (^) Tp +A (^) p E (^) satp L (^) p
= – , t 2 < t < t 3 ,t 4 < t <t 5
The average short circuit power dissipation is
P (^) sc
T (^) sw
-------- (^) ( I (^) Dp V (^) DSp +I (^) Dn V (^) DSn) dt 0
T (^) sw
T (^) sw
-------- I
D p n
T (^) sw
but the circuit is constructed so that
- V (^) DSp + V (^) DSn = V (^) dd.
Therefore,
P (^) sc
V (^) dd T (^) sw
-------- I
D p n
dt 0
T (^) sw
V (^) dd T (^) sw
-------- I (^) Dn t I (^) Dp dt t 2
t 3
t d +^ ∫
1
t 2
∫ t I^ Dp^ dt
4
t 5
∫ tI^ Dn^ dt
5
t 6
The time dependence enters into IDn and IDp only through Vin(t) during the times needed
for the integrals. Vin(t) varies linearly with time over these periods (assuming a smooth
ramp input) so that the integrals over time can again be changed to integrals over voltage.
… dt t 1
t 2
∫ …^
d t
dV (^) in
---------------- (^) dV (^) in V (^) in (t 1 )
V (^) in (t 2 )
where
d t
dV (^) in
V (^) dd t (^) r
-------- ,t 1 < t <t 3
V (^) dd t (^) f
The first integral in the expression for Psc is
V (^) dd T (^) sw
-------- (^) I (^) Dn dt t 1
t 2
V (^) dd T (^) sw
βn 2
E (^) satn L (^) n ( V (^) in – V (^) Tn) 2
( V (^) in – V (^) Tn) +A (^) n E (^) satn L (^) n
dV (^) in V (^) dd ⁄t (^) r
V (^) Tn
V (^) inv
t (^) r T (^) sw
=^ --------^ ⋅ G (^) n (V (^) inv – V (^) Tn) ⋅V (^) dd^2
where
G (^) n (V )
βn E (^) satn L (^) n
2 V (^) dd^2
------------------------ V
2
2
------ (^) – A (^) n E (^) satn L (^) n V ( A (^) n E (^) satn L (^) n)^2 1 V A (^) n E (^) satn L (^) n
+^ ------------------------
The other integrals can be evaluated in a similar fashion so that
P (^) sc
t (^) r +t (^) f T (^) sw =^ -------------^ [ G (^) n (V (^) inv – V (^) Tn) +G (^) p (V (^) dd – Vinv – V (^) Tp)]V (^) dd^2
where
G (^) p (V )
βp E (^) satp L (^) p
2 V (^) dd
V
2
2
------ (^) – A (^) p E (^) satp L (^) p V ( A (^) p E (^) satp L (^) p)^2 1 V A (^) p E (^) satp L (^) p
+^ ------------------------
If we rewrite the short circuit power in terms of the switching frequency, αf, as before
P (^) sc = (t (^) r +t (^) f) [ G (^) n (V (^) inv – V (^) Tn) +G (^) p (V (^) dd – Vinv – V (^) Tp)]V (^) dd^2 αf
we see that it has the same frequency dependence as the dynamic capacitive switching power, Pd, but it is also proportional to the rise and fall times of the input waveform (not
the output). The short circuit power is completely wasted whereas the dynamic power, Pd,
is consumed while doing useful work driving the output capacitance. The input rise and fall times should be kept short enough so that Psc<< Pd which implies that
t (^) r + t (^) f
C (^) load G (^) n (V (^) inv – V (^) Tn) +G (^) p (V (^) dd – Vinv – V (^) Tp)
This relation can be written in a more useful form if we replace Cload by the rise and fall
times at the output (the rise and fall times we have been discussing are the rise and fall times at the input).
t (^) r out( ) + t (^) f out( ) = 2 (R (^) onp +R (^) onn)C (^) load
which gives
t (^) r out( ) +t (^) f out( ) t (^) r in( ) +t (^) f in( )
--------------------------------- (^) » 2 ( R (^) onp +R (^) onn) [ G (^) n (V (^) inv – V (^) Tn) +G (^) p (V (^) dd – Vinv – V (^) Tp)]
be found that meets a maximum allowable delay constraint and a maximum allowable power constraint.
W
td (^) P
tdmax Pmax
minimum power feasible solutions for W minimum delay
Within the feasible range, the larger widths give smaller delay and the smaller widths give smaller power. The picture above is for a single width; the general solution must be obtained in multidimensional W-space where there is a dimension for each transistor width. This is a difficult problem in non-linear constrained optimization.
Power/Ground Line Sizing
Sizing power and ground lines is done with different criterion than normal signal wires. The power and ground lines carry much higher currents than signal wires because the cur- rent passing through every gate in the chip must eventually come through the power and ground nets. Also, the power and ground lines are supposed to stay at a constant voltage and therefore may have a large capacitance. This allows very wide metal lines to be used to handle the large currents. The metal lines must be wide enough to handle the metal migration and ohmic drop problems discussed below.
Metal Migration. Aluminum is used almost always to form the metal lines in integrated circuits. The metal atoms are bound very loosely in solid aluminum. It is possible for the metal atoms to be knocked out of their normal position by the conduction electrons collid- ing with the atoms. Once an atom is moved from its original position, the wire becomes slightly thinner at that point.
I metal atom
This increases the current density at that point which makes it more likely that another atom will be knocked away in the same vicinity. An open circuit failure can eventually be produced if enough metal atoms are moved. This phenomenon is called metal migration.
Metal migration occurs above a critical current density of about Jmm = 1mA/μm^2 in alumi-
num.
Wm I (^) t
t: = metal line thickness (process constant)
I
W (^) m t
---------- (^) <J (^) mm
or
W (^) m
I
J (^) mm t
>^ -----------
Typically,
0.5μm < t <1.0μm so that
W (^) m (1 2 , ) μm mA
> ---------^ ×I
The current is usually estimated from the dynamic power dissipation.
I
P (^) d V (^) dd
-------- (^) αgate C (^) gate V (^) dd f gates
where the summation is over the gates that draw current through that section of the power or ground line.
Ohmic Voltage Drop.
Vdd
GND
circuit
I
I
∆V = RI
We want the ohmic voltage drop, ∆V , to be a small fraction of the power supply voltage,
Vdd. Let’s choose ∆V < 0.1V (^) dd. Then
