SCORE:________ Name:__________________________________________
ECE 4100/6100 Advanced Computer Architecture
Exam III – Summer 2004
1. (10 points) What limits the size and complexity of the L1 cache and why is an L2 (and even an L3) in
common use today?
The L1 cache is in the critical delay path for clock cycle time on most processors. If it gets too large
(larger memory is slower) everything else would slow down. Adding larger L2 or L3 cache levels keeps
L1 hits as fast as possible and reduces the miss penalty on an L1 miss.
2. (10 points) List the five approaches suggested in the text to reduce the cache miss penalty.
Write Policy
Read Priority over write on a miss
Early Restart – Critical Word First
Non Blocking Caches
Add an additional level of cache
3. (10 points) Other than increasing cache size, associativity or number of levels how can you reduce the
bad effects of cache conflicts (in hardware and software)?
Hardware: Victim Cache
Software: compiler optimizations to reduce conflicts
4. (15 points) A computer has three levels of cache. The L1 cache has a 8% local miss rate and the L2
cache has a local miss rate of 30%. The global (L1,L2,L3 combined) cache system hit rate is 98%. Main
memory takes 50 clock cycles at 4Ghz, an L3 hit is 20 clock cycles, an L2 hit is 8 clock cycles, and an L1
hit is 2 clock cycles. Compute the average memory access time.
Need L3 hit/miss rate: ML1*ML2*ML3= Global miss rate, .08*.30*ML3 = 100-98, so ML3=.833
AMAT=HTL1+MRL1*(HTL2+MRL2*(HTL3+MRL3*Mem))
AMAT = 2+ .08*(8 + .3 * (20 + .833*50) = 4.12
4.12/4Ghz = 1.03 ns.
Average memory access time = _____4.12______clocks and _____1.03___________ ns.
