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Practice Midterm II Super Exam
Nov. 14, 8:35-9:25am
Name:
(98 points total)
Problem 1: A feedback amplifier employing series-shunt feedback is shown in Fig. 1, where the feedback network is contained within the dotted line. The compo- nent values are Rs = 1 kΩ, Rin = 10 kΩ, Ro = 100 Ω and RL = 10 kΩ, and A = 10,000 V/V for the basic amplifier. [13 points]
(a) What type of 2-port network parameters should be used to model the feedback network? [1] (b) Calculate the relevant 2-port network parameters for the feedback network. [4] (c) Calculate the forward gain of the amplifier with the feedback network load- ing effects included. [4] (d) Use the results from the previous parts to calculate the input resistance with feedback, Rif , as denoted in Fig. 1. [4]
Figure 1: Series-Shunt feedback amplifier.
Problem 1 (cont’d)
Problem 2 (cont’d)
Problem 3: A feedback amplifier employing series-series feedback is shown in Fig. 2, where the feedback network is contained within the dotted line. The compo- nent values are Rs = 1 kΩ, Rin = 10 kΩ, Ro = 10 kΩ and RL = 5 kΩ, and A = 100 A/V for the basic transconductance amplifier. [13 points]
(a) What type of 2-port network parameters should be used to model the feedback network? [1] (b) Calculate the relevant 2-port network parameters for the feedback network. [4] (c) Calculate the forward gain of the amplifier with the feedback network load- ing effects included. [4] (d) Use the results from the previous parts to calculate the gain with feedback, Af = Io/Vs, as denoted in Fig. 2. [4]
Figure 2: Series-Series feedback amplifier.
Problem 4: We wish to digitize a signal with a full-scale range from 0-5 V. We would like the quantization error of the digitized signal to be less than 0.05 V. [10 points]
(a) How many bits are required for the ADC? [2] (b) What is the size of one LSB for the resulting ADC? [1] (c) If the ADC is implemented using a dual-slope ADC (as shown in Fig. 3) with R = 1 kΩ, C = 3.95 nF, and fclk = 10 MHz, what is the maximum possible value of VP EAK? [4] (d) What is the maximum sample rate for this ADC? [3]
Figure 3: Dual-slope ADC.
Problem 4 (cont’d)
Problem 6: We wish to design a CMOS logic gate to implement the function Y = (A + B) · C. [12 points]
(a) Draw the logic gate. [4] (b) With the assumption that μn = 6 × 10 −^2 m^2 /Vs and μp = 2 × 10 −^2 m^2 /Vs, size the transistors to provide equal worst-case drive strengths for the pull- up network and pull-down network. [4] (c) With Cox = 2 × 10 −^3 F/m^2 , what would the dynamic power consumption be of the circuit driving the A input at 10 MHz? Assume L = 1μm for all devices and VDD = 5 V. [4]
Problem 7: The same designer who provided us with the ill-fated modified CMOS inverter that we analyzed in class has come up with another inverter architec- ture, shown in Fig. 5. Despite our skepticism, we have decided to review his latest chef-d’oeuvre. Assume that VDD = 5 V for this process, and the device threshold voltages are Vtn = Vtp = 1 V. [12 points]
(a) Draw the voltage transfer characteristics (VTC) for this gate in the space provided, and indicate which operating region each transistor will be in at different segments of the curve (hint: there should be 5 distinct segments). [8] (b) Find the threshold voltage for the gate, under the assumption that both devices are in saturation at this point, and the devices have been sized for equal drive strength. [4]
Figure 5: Modified CMOS inverter.
Problem 8: Consider a standard CMOS inverter with power supply VDD = 5 V, implemented in a process with Vtp = Vtn = 1 V, μn = 5 × 10 −^2 m^2 /Vs, μp = (^2) (. 5 × 10 −^2 m^2 /Vs, and Cox = 2 × 10 −^3 F/m^2. The devices are sized with W L
) n = 1 and
( W L
) n = 2. [12 points]
(a) What is the low noise margin (N ML) for this inverter? [1] (b) What is the propagation delay for the inverter, assuming it drives a load of C = 10 fF? [2] (c) What is the maximum clock speed for a logic chain consisting of ten in- verters in this technology? [2] (d) What is the total power consumption of a chip with 100,000 gates, each with a probability of switching of 0.25 on any given clock cycle (assume each gate drives a 10 fD load, and the clock speed is the value calculated in (c))? [2] (e) We now wish to scale back the power supply voltage to reduce the power consumption, how much can we reduce VDD and still maintain a clock speed greater than 1.8 GHz? [3] (f) How much will this extend the battery life? [2]
