Program Interrupts - Lecture Slides | ELEC 2220, Study notes of Electrical and Electronics Engineering

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Program Interrupts

Chapter 12

Program interrupts

 An “event” interrupts a running program to

force execution of another program

 Signal from an external device

 Signal from an internal device

 Exceptional condition (ex. divide by 0)

 Software interrupt instruction (swi)

 CPU executes an “interrupt service routine”

to deal with the interrupt event

Asynchronous events (Fig. 12-2)

Timeline:

Expanded Timeline:

 Signals from external devices on designated

CPU pins

IRQ (interrupt request) pin

XIRQ (non-maskable interrupt request) pin

 Signals from internal functions

 Timers

 Communication channels

 Detected failures (clock, illegal instruction,etc.)

 Software interrupt instruction (SWI)

HCS12 interrupt sources

Enabling/disabling interrupts

Disble IRQ: ORCC #%00010000 (formerly SEI)

Enable IRQ: ANDCC #%11101111 (formerly CLI)

Enable XIRQ: ANDCC #%

S X H I N Z V C

Mask XIRQ Mask IRQ

1 “masks” (disables) IRQ/XIRQ

0 “unmasks” (enables) IRQ/XIRQ [default state]

X bit cannot be set to 1 after it has been cleared.

Therefore, once enabled, XIRQ cannot be disabled.

Condition Code Register (CCR)

CPU actions in an interrupt sequence

1. Check interrupt signals after completing

current instruction

2. Determine address of interrupt service

routine (interrupt vector)

3. Push PC (return address) on stack

4. Push X, Y, A, B, CCR onto stack

5. Set I bit in CCR (mask other interrupts)

6. Branch to interrupt service routine

Interrupt vectors

 “Interrupt vector” = start address of interrupt service

routine

 Interrupt vectors for all interrupt sources are stored

in the last bytes in memory

Examples:

FFFE,FFFF: Reset vector

FFFC,FFFD: Clock monitor fail (reset) FFFA,FFFB: COP failure (reset) FFF8,FFF9: Unimplemented opcode trap FFF6,FFF7: SWI FFF4,FFF5: XIRQ pin

FFF2,FFF3: IRQ pin FF00…FFF1: Built-in functions (device-specific)

Interrupt vector assignments for HCS

Continued on next slide

Creating the reset vector

(Code Warrior sample program)

; code section ORG ROMStart Entry: LDS #RAMEnd+1 ; initialize the stack pointer CLI ; enable interrupts mainLoop: …….

;************************************************************** ;* Interrupt Vectors * ;************************************************************** ORG $FFFE ; Address for storing reset vector DC.W Entry ; Reset Vector

Initializing HCS12 Interrupt Vectors

; Initialize Timer Channel 0 Interupt vector

TC0 EQU $FFEE ; Address of the vector

; Put in the main program

ORG ROMstart

Entry: (main program)

; The interrupt service routine starts with a label

; at the first instruction to be executed

TC0ISR:

Timer ISR Instructions rti ; The isr ends with a RTI

; Locate the vectors

ORG TC DC.W TC0ISR ; The label is the address of the ISR ORG $FFFE ; Address of reset vector DC.W PROG

Highest priority interrupt register

(HPRIO)

PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0

• To dynamically change interrupt priorities of

IRQ and lower-priority interrupts

• Promote any one interrupt to “highest priority”
• Write 7-bit code (from Table 12-1) to HPRIO
• Should be done with CCR I bit set

Example

Write a small segment of code to raise Timer Channel 2 to the highest priority

position.

hprio1c.asm Assembled with CASM 05/28/1998 02:20 PAGE 1

0000 1 HPRIO: EQU $1F ; HPRIO address 0000 2 TC2VECT: EQU $FFEA ; Channel 2 Vector 3 ;... 4 ; Mask interrupts while setting HPRIO 0000 1410 5 sei ; Set I-bit 6 ; Raise Timer Channel 2 to the highest priority 0002 CCFFEA 7 ldd #TC2VECT 0005 5B1F 8 stab HPRIO 0007 10EF 9 cli ; Clear interrupt mask

hprio1c.asm Assembled with CASM 05/28/1998 02:20 PAGE 1

0000 1 HPRIO: EQU $1F ; HPRIO address 0000 2 TC2VECT: EQU $FFEA ; Channel 2 Vector 3 ;... 4 ; Mask interrupts while setting HPRIO 0000 1410 5 sei ; Set I-bit 6 ; Raise Timer Channel 2 to the highest priority 0002 CCFFEA 7 ldd #TC2VECT 0005 5B1F 8 stab HPRIO 0007 10EF 9 cli ; Clear interrupt mask

Interrupt control register (INTCR)

IRQE IRQEN DLY 0 0 0 0 0

• IRQE (IRQ edge-sensitivity)
  • 1 => IRQ responds only to falling edges
  • 0 => IRQ responds only to low levels
• IRQEN (IRQ enable)
  • 1 => IRQ pin connected to interrupt logic
  • 0 => IRQ pin disconnected from interrupt logic

•DLY : oscillator startup delay on exiting “stop mode”

• 1 => delay
• 0 => no delay

RESET Values: 0 1 1 0 0 0 0 0

Example: Interrupt-driven printing

DATA8-

STRB*

BUSY

ACK*

PA7-

PB 0

PB 1

IRQ

Printer

DATA8-

STRB*

BUSY

ACK*