Programming Model, Address Mode, HC12 Hardware Introduction | EEL 4744, Study notes of Microprocessors

Material Type: Notes; Professor: Li; Class: MICROPROCESSOR APPLIC; Subject: ENGINEERING: ELECTRICAL; University: University of Florida; Term: Unknown 1989;

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Dr. Tao Li 1
EEL 4744C: Microprocessor Applications
Lecture 2
Programming Model, Address Mode,
HC12 Hardware Introduction
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Download Programming Model, Address Mode, HC12 Hardware Introduction | EEL 4744 and more Study notes Microprocessors in PDF only on Docsity!

EEL 4744C: Microprocessor Applications

Lecture 2

Programming Model, Address Mode, HC12 Hardware Introduction

  • Microcontrollers and Microcomputers: Chapter 3,

Chapter 4

  • Software and Hardware Engineering: Chapter 2

Or

  • Software and Hardware Engineering: Chapter 4

Plus

  • CPU12 Reference Manual: Chapter 3
  • M68HC12B Family Data Sheet: Chapter 1, 2, 3, 4

Reading Assignment

• Accumulators

  • Registers that accumulate answers, e.g. the A Register
  • Can work simultaneously as the source register for one operand and the destination register for ALU operations

• General-purpose registers

  • Registers that hold data, work as source and destination register for data transfers and source for ALU operations

• Doubled registers

  • An N-bit CPU in general uses N-bit data registers
  • Sometimes 2 of the N-bit registers are used together to double the number of bits, thus “doubled” registers

CPU Registers

• Pointer registers

  • Registers that address memory by pointing to specific memory locations that hold the needed data
  • Contain memory addresses (without offset)

• Stack pointer registers

  • Pointer registers dedicated to variable data and return address storage in subroutine calls

• Index registers

  • Also used to address memory
  • An effective memory address is found by adding an offset to the content of the involved index register

CPU Registers (2)

• MOV A, B

  • B is the source, A is the destination

• ADD A, B

  • Add (A) to (B), then transfer the answer from ALU to

A

• Register transfer language

  • Register name in () means “content” of the register
  • “” means replacement, e.g. (A)  (B)

Register Transfers

• Also called flag or status registers

• Contain bits that are set or reset due to

instructions

  • ALU, load or move can all modify the CCR

• Most processors also provide instructions that

modify the CCR directly

• What are the “bit” in the CCR?

Condition Code Register (CCR)

• Carry bit for multiple-byte ADD/SUB

  • Carry from the less significant bytes is added into

the ADD/SUB of the next more significant bytes

• Example: 00110010 11001001 + 00011011 10110110

  • A carry of 1 from the LSB’s is added into the MSB’s

• What if we try to add two numbers that are

encoded in 2 ’s-complement bits?!

• Example: 10010011 (-

10

10

  • Give 1 01000110 (- 10

) and 1 11100000 (-

10

  • The ADD results in overflow, the SUB has no

problem

Condition Code Register (3)

• Conclusion: carry/borrow bit can not be used to

indicate overflow/underflow for 2’s-complment!

• A separate bit is needed to indicate overflow for

2 ’s-complement numbers

  • Overflow occurs if the 2 operands have the same sign AND the result is of different sign
  • Overflow cannot occur if the 2 operands have opposite signs
  • Which one is the sign bit? The most significant bit, not the carry/borrow bit

Condition Code Register (4)

• Sign bit

  • Most significant bit of the number (not the carry bit)
  • Gives the sign only of signed number encoding is used

• Zero bit

  • Set to 1 if the result of an operation equals to zero
  • Otherwise it is reset to 0 or false

• Parity bit

  • Even-parity: set if result has an even number of 1 ’s
  • Odd-parity: set if result has an odd number of 1 ’s
  • Useful for checking errors in long-haul data transmission
  • Parity-even/parity-odd works with conditional branches

Condition Code Register (6)

• Symbols for flags

  • Carry: C
  • Overflow: V
  • Sign: S
  • Zero: Z
  • Parity: P

• Using the CCR

  • CCR is attached to the sequence controller
  • For use by the conditional branch instructions
  • Results of operations will set or reset C, V, S, or Z
  • Conditional branch instructions checks C, V, S, or Z

Condition Code Register (7)

EEL 4744C: Microprocessor Applications

Lecture 2

Part 2

Addressing Modes

• Physical address

  • The actual address supplied to the memory
  • Number of bits in physical address determines the maximum number of memory locations that can be addressed

• Segment address

  • Gives the location of a segment of memory (e.g. block, page, etc.) that is smaller than the full memory

• Offset address

  • One that is calculated from the start of a segment of memory

Addressing Terminology

• RAM

  • Stands for random access memory
  • Memories that can be read from and written to

• ROM

  • Stands for read only memory

• Memory map

  • Shows which addresses are used for which purposes
  • May show which addresses contain ROM, RAM, and

which have no memory installed at all

• I/O map

  • Similar to a memory map for I/O functions

Addressing Terminology (3)

• Linear addressing

  • Instructions specify the full physical address
  • Favored by Motorola processors
  • Motorola MC68020 used 32-bit addresses, giving a

4GB addressable memory size

Memory Architectures

Linear addressing memory map for an n-bit address