CDA 4150-Lab 3/1
CDA 4150 Project 3
Adding Caches to the Processor Model
DueThurssday,November4th,1:30pm
Computer Systems Laboratory, University of Central Florida Orlando, FL 32816.
1. Objective
The purpose of this lab is to add both a data cache (D$) and instruction cache (I$) to your pipelined
processor model. You will be given two Verilog models—a working pipelined model and a pipelined model
with support for caching. The latter model is not complete and it is your assignment to complete it. The
former model can be used at your discretion as a “gold standard”. It may be useful to instrument the
working version and use it to compare your cache version against when debugging. Neither version has a
multiply/divide unit. You may add those in as a part of the extra credit.
After adding the caches, there are 3 extra-credit sections in the lab. These are completely optional, and
are discussed at the end of this handout.
2. Lab Setup
•Go to your home directory (type cd)
•mkdir cda4150/lab3
•cd !$
•cp ~heinrich/cda4150/lab3.tgz .
•Uncompress the file with tar -xzf lab3.tgz
•You should now have a pipe/ and a pipe+cache/ directory
The pipe/ directory is the working MIPS pipelined model. It is a solution to lab2 (w/o a multiply/divide
unit). Please be sure you check out the solution and understand the material from lab2. The pipe+cache/
directory is the working directory for lab3 that contains the incomplete cache model.
3. Adding the Caches
The goal of this lab is to add an 8KB direct-mapped, 32B line, I$ and an 8KB direct-mapped, 32B line,
writeback D$ to the processor model in the pipe+cache/ directory. The caches have already been created
via a special PLI routine in an initial block in mips.v. A later section describes all the new PLI routines in
detail.
To implement a correct solution for this lab, you should need only to change the mem.v file. However,
do not be misled. The additions to this file can be difficult and numerous. In addition, although you do not
need to modify the other files in the processor, mips.v and cpu.v have changed significantly with respect to
the pipe/ model. These changes are intended to simplify the lab, and allow you to focus on implementing
the cache control in mem.v.
3.1. The Memory System
mips.v is heavily changed from the previous labs. The main difference is that the processor/memory
interface changes considerably when the processor has on-chip instruction and data caches. In particular,
there is no need to have separate address and data busses for instructions and data. Instead, there is just
Tuesday, Dec 1st, 11:59pm
cp ~hgao/cda4150/lab3.tgz .
