Project Specification for VHDL Implementation | ECE 746, Study Guides, Projects, Research of Electrical and Electronics Engineering

Download Project Specification for VHDL Implementation | ECE 746 and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity!

ECE 746

Project Specification for VHDL

implementation

of

HMAC using SHA-

By

Tapan Desai and Roar Lien

For the attention of :

Dr. Kris Gaj.

Target Entry Method

The design entry method is VHDL. Active HDL 5.1. Xilinx ISE 4 will be used for design specification and implementation. For experimentally testing the design we will be using SLAAC1-V FPGA accelerator boards, based on Xilinx Virtex 1000 devices.

Additional Libraries

1. Additional library of basic digital circuits required in the design is Xilinx

LogiBlox.

I/O Specification

2. Inputs : i. A Key (K) of 64 bytes. ii. A message (M) of size [(2^64 bits-1) – 64 bytes] Output: i. A digest of size 160 bits.

Circuit Functions and Algorithms

3. Let H be the hash function SHA-1. The function HMAC takes the key K and a message M, and produces HMACk (M))=H(K XOR opad, H(K XOR ipad, M)), where ipad, and opad are 64 byte constants of 0x36 and 0x5C respectively. Note that in the function H(K XOR ipad, M) the message M is concatenated to (K XORipad). Implementation of SHA-1 will be as specified by the Secure Hash

This module performs the necessary functions (defined below) on each round and also makes use of an additive constant Kt , defined in the table below. Step Constant Kt Function

0<=t<=3 Kt =5A827999 f 1 =f (t,B,C,D) = (B AND C) OR (NOT B AND D) 4<=t<=7 Kt =6ED9EBA1 f 2 =f (t,B,C,D) = B XOR C XOR D 8<=t<=11 K t =8F1BBCDC f 3 =f (t,B,C,D) = (B AND C) OR (B AND D) OR 12<=t<=15 Kt =CA62C1D6 f 4 =f (t,B,C,D) = B XOR C XOR D

Table 1.1:List of Constants and Functions Used In Iterations

Once all 512-bit blocks have been processed, the output from the final stage is the 160-bit message digest.

Procedures For Testing Functionality and Performance of Circuit(s)

4. Procedures for testing the functionality and performance of the circuits at gate level include: i. Simulator: Active HDL 5. ii. Source of test vectors: As specified by Appendix A and B of the following URL, http://www.itl.nist.gov/fipspubs/fip180-1.htm to enable verification of functionality. iii. Format of input stimuli: VHDL test bench and an input file into the FPGA chip. iv. Performance parameters (simulation): Projected throughput is 1 Gbits/s.

v. Parameters (implementation): minimum size FPGA device able to hold the device, area of the circuit in the standard-cell implementation and maximum clock frequency of the circuit.

Plan of Simulation Experiments On Circuits

5. Procedure for simulation of circuit includes: i. Develop correctly functioning VHDL code using only the VHDL Synthesis Subset Xilinx ISE 4. ii. Test functionality of synthesized VHDL code with timing constraints on SHA-1 implementation. iii. Test functionality of synthesized VHDL code with timing constraints on HMAC implementation. iv. Test functionality of generated bit stream of SHA-1 implementation. v. Test functionality of generated bit stream of HMAC implementation. vi. Timing analysis of generated bit stream of SHA-1 implementation. vii. Timing analysis of generated bit stream of HMAC implementation.

Time Schedule

6. The Gantt timeline in figure 1.1 shows tasks to be completed and summarizes the deadlines to accomplish this project. Individual tasks are specified on a weekly basis and are shown in a logical order.

iv. C. P. Pfleeger, Security in Computing, 1997 Prentice-Hall, Inc. Upper Saddle River, New Jersey 07458. 2 nd Edition. ISBN 0-13-337486-

Note that the above list is not exhaustive and more will be added as required.