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Some keywords in Digital Principles are Cmos Nand Gate, Linearity E, Nand Gate, Power Dissipation, Single-Slopeanalogue. Main points of this past exam are: Propagation Delay, Noise Margin, Fan-Out, Power Dissipation, Circuit, Logic-Level Combinations, Operation
Typology: Exams
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Semester 2 Examinations 2011/
Module Code: ELTR
School: School of Electrical & Electronic Engineering
Programme Title: Bachelor of Engineering in Electronic Engineering Bachelor of Engineering (Honours) in Electronic Systems Engineering
Programme Code: EELXE_7_Y EELES_8_Y
External Examiner(s): Mr. I. Kennedy, Dr. A. Donnellan Internal Examiner(s): Jerome O’Driscoll
Instructions: Answer all questions. All questions carry equal marks
Duration: 2 hours
Sitting: Summer 2012
Requirements for this examination:
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
Q1. (a) With reference to the TTL logic families, explain [with diagrams where appropriate] the following terms:
(i) noise margin [2 marks] (ii) fan-out [2 marks] (iii) propagation delay [2 marks] (iv) power dissipation [2 marks]
(b) Figure 1 shows the circuit diagram of a standard 7400 TTL 2-input NAND gate. Assuming inputs A and B may be either 0 V (logic-0) or +5 V (logic-1), describe its operation for all possible logic-level combinations of A and B. [9 marks]
Figure 1
(c) Indicate how the circuit in Figure 1 may be modified to (i) reduce the power dissipation ( PD ), (ii) reduce the propagation delay ( tp ). [4 marks] Briefly explain how the modifications would work. [4 marks]
Q2. (a) Briefly explain why a JFET (junction FET) is not a suitable device for use in digital circuits. [5 marks]
(b) Figure 2 shows the circuit diagram of a CMOS digital logic gate. What logic function does the gate perform? [4 marks] Describe the operation of the logic gate. [8 marks]
(c) Figure 3 shows a level-translator circuit to interface the output of a TTL logic gate to the input of a high-voltage CMOS logic gate. Describe its operation. [8 marks]
Figure 4
Q4. (a) A photodiode has two modes of operation, photoconductive and photovoltaic. Describe its operation in both modes. [3 marks] Indicate one practical application for each mode of operation. [3 marks]
(b) When a light beam illuminates the photoconductive cell in Figure 5, its resistance is 20 kΩ. The dark resistance of the cell is 100 kΩ. Show that the relay is de-energised when the cell is illuminated and energised when the light beam is interrupted. [10 marks]
Figure 5
Q4. (c) An array of solar cells is to be constructed so it will deliver 4 A at 6 V under a certain light intensity. If each cell delivers 0.8 A at 0.6 V under the given intensity, deduce the following: (i) How many cells will be required. [3 marks] (ii) How the cells should be connected. [3 marks]
Draw the circuit diagram. [3 marks]
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