Quantum Random Number Generator - Project 18 Report | ECE 445, Study Guides, Projects, Research of Electrical and Electronics Engineering

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QUANTUM RANDOM NUMBER GENERATOR

By Adam Petschke Jeff Kramer ECE 345, SENIOR DESIGN PROJECT FALL 2004 TA: Spencer Hoke May 4, 2004 Project No. 18

ABSTRACT

The purpose of this project is to create a circuit that drives an LED with a specified current. The current is probabilistically balanced such that when the light output is attenuated to a single photon, the probability that a photon hits a detector within a given period is constant. The time that the photon hits is considered the random variable. This circuit has applications in quantum cryptography. ii

1. INTRODUCTION

There are two requirements for secure data transmission. The first is the secure transmission of the encryption key. One possibility for this transmission is to use quantum particles. The second requirement is an encryption key that consists of random bits. Currently, quasi-random numbers are generated with a random number algorithm. 1.1 Quantum Cryptography Quantum cryptography is the area of communications concerned with using quantum systems to encrypt data. It is based on the fundamental postulate of quantum mechanics that states a measurement of a quantum system will change that system. The most common particles used are photons mainly because they can be sent one at a time through a fiber optic cable rather easily. The photons are polarized in two different directions which represent a 1 and 0. Briefly, the photons are polarized randomly and sent to the receiver. If the photons are looked at in any way, they will be altered and, hence, the receiver will know not to use that bit. This concept will only work, however, if the photons are polarized randomly. One idea for creating truly random numbers is to use a physical process that is random [1]. 1.2 Review Our project uses photon emission as the random process. The idea is to send a specific current through an LED such that the light output of the LED is probabilistically balanced. This means if the light is attenuated down to a single photon, the probability the photon hits a detector during some time period, T, is constant. The required current is derived in Appendix 1 and is repeated below as equation 1.1. I  1 /( T  t ) (1.1) It should be noted that this function goes to infinity as t goes to T. Therefore, it is impossible to generate this current exactly. This raises the issue of where to truncate the function and what this truncation does to the overall randomness of the project. It turns out that no matter where you truncate the function, the overall randomness of the project is conserved. The only loss is overall speed. For example, if the truncation is at T/2 the speed will be cut in half. We chose 0.9T as a reasonable truncation because the speed is not reduced too much and the slope is not too steep before this point. The random number is generated by a counter which is not part of this project. The random variable is the time at which the photon hits the detector. 1.3 Specifications  Frequency of operation is at least 1 MHz  Shutdown must occur within 100 ns of photon reception  Photon output is 630 nm  Temperature sensitivity is at a minimum The first specification requires T to be 1 us or less. The second specification is required because the photodetector used in the final implementation (with single photons) can only handle a certain number of photons in a given time period. Although our project is only concerned with generating the required light output and not single photon detection, the shutdown circuit is essential for the final implementation of this project. The third specification is required so the photon wavelength matches the sensitivity of the single photon detector. The last specification is met by driving the LED with current as opposed to voltage so the exponential dependence on temperature is eliminated. This can be seen with equation 1.2 which is the diode I-V equation with A(T) a parameter with a temperature dependence.

VA ( T ) I I S e   (1.2) 1.4 Block Diagram Figure 1. Block Diagram The block diagram is relatively simple. The probability circuit generates the required current to drive the LED. The shutdown circuit stops the current within 100 ns of photon detection by the detector. The output is sent to a counter which generates the random number based on the time the photon hits the detector.

2. DESIGN DECISIONS

Probability

Circuit

LED Detector

Shutdown

Circuit

Optical

Path

Output

3.1 Components We chose the digital system as our final design path. The schematic below is our final design that was constructed on our protoboard (Figure 3.1, see on next page). In order to implement this system, we chose an FPGA, the XSA-100 [2], as our digital controller. This system approximates what our desired final solution is: a system on a chip. It also is easy to program and easy to use in a mixed environment (both digital and analog). The XSA-100 runs at a maximum speed of 100 MHz, yet it was necessary for us to reduce this to be able to use the rest of the components in our system on such a short schedule. The FPGA contains both a counter and a set of data points within its memory. At runtime, the FPGA steps through these data points using the counter, outputting an 8-bit wide digital signal, as shown in Figure 3.1. This digital signal is the digital representation of our final curve. By directly manipulating the curve, the system can be easily tuned and changed to suit changing specifications or to fix errors. After analyzing the curve computed above, we determined a set of 10 data points and stepped through them, dumping the output on the lines to the DAC. The code for this processor is in Appendix 2. The DAC we chose was the DAC 0800 [3], a very ubiquitous model. However, this DAC fits most of our needs and was very cheap. The output from the FPGA is turned into a true analog signal in this component. The output of the system runs between +(Input Voltage)  -(Input Voltage). In our case, we used the lowest input voltage possible, 5 volts. This gave us much tighter control over the output of the system to the LED, as there was less of a voltage range to vary our 256 values over. However, the DAC was not designed to source power to an LED, so we found that we required a LED driver, built from an op-amp. This LED driver/OpAmp provided all the needed power in order to run the LED. We used a LM318 OpAmp [4] to build this circuit, as the op-amp speed was the fastest we could find, save ordering special chips from third party manufacturers. Also, the voltage output was excellent (+/- 15V). The choice of LED also required careful consideration. Our specifications required an LED operating in the 630 nm spectrum. Our LED [5] runs at exactly 633 nm. The LED’s specifications, as seen below in Figure 3.2, are an important part of the initial curve generation. By feeding this system back into the main system curve, we can determine the real final curve. The LED was also chosen for its near linear operation in both systems. The shutdown circuit was implemented internally to the FPGA, via an input bit that shuts off the output of the FPGA. Much of the design was completed while working on some of the previous designs. One of these completed designs was a photodetector circuit utilizing the J16R01M18A [6] Ge Photodiode. This photodiode was sensitive, yet wideband enough to capture the required light from our not so ideal set up.

Figure 3.1 Schematic for Final Digital Design Figure 3.2 LED Specifications

Figure 4.2 Photodetector Output Figure 4.3 Photodetector Output with superimposed curve

Table 4.1 Data point variation

• 1. INTRODUCTION....................................................................................................................
  • 1.1 Quantum Cryptography......................................................................................................
  • 1.2 Review................................................................................................................................
  • 1.3 Specifications......................................................................................................................
  • 1.4 Block Diagram....................................................................................................................
• 2. DESIGN DECISIONS..............................................................................................................
  • 2.1 Analog Circuits...................................................................................................................
  • 2.2 Digital Circuit.....................................................................................................................
• 3. DESIGN DETAILS..................................................................................................................
  • 3.1 Components........................................................................................................................
• 4. DESIGN VERIFICATION.......................................................................................................
  • 4.1 Testing................................................................................................................................
• 5. COST........................................................................................................................................
• 6. CONCLUSIONS....................................................................................................................
  • 6.1 Accomplishments.............................................................................................................
  • 6.2 Recommendations.............................................................................................................
  • APPENDIX 1. DERIVATION OF REQUIRED CURRENT................................................
  • APPENDIX 2. FPGA CODE.................................................................................................
  • REFERENCES.......................................................................................................................
• Data Point Difference (mV) Difference^2 (V)^
  • 1 30 0.
  • 2 50 0.
  • 3 50 0.
  • 4 200 0.
  • 5 300 0.
  • 6 400 0.
  • 7 500 0.
  • 8 600 0.
  • 9 900 0.

6. CONCLUSIONS

6.1 Accomplishments We met three of the design criteria: shutdown within 100 ns, minimal temperature sensitivity, and correct output wavelength. However, we had several problems: frequency of operation too slow and circuit noise. There are two reasons the operation is too slow. The first is our design is digital which means the output from the FPGA is updating at a faster rate than the overall frequency. This is a design problem but could be improved by using a printed circuit board. However, the circuit board would have to be matched and be at least 4 layers to isolate the analog and digital power and ground. This would be relatively expensive compared to an analog implementation. The other reason the circuit is slower than specifications is the photodetector could not handle a faster speed. This problem would be eliminated in the final implementation of this project, however. The solutions mentioned above would also reduce circuit noise. 6.2 Recommendations We recommend that the final implementation be an analog circuit. The first reason we recommend this is the circuit could be made fast enough while still being tested on a protoboard. The second reason is the cost is much lower. The third reason is the design is greatly simplified and because of this the overall circuit will be more accurate. If price was not an option, however, we would recommend this circuit be implemented as a digital system on an IC chip. In this case only, the digital system would be very accurate.

APPENDIX 1. DERIVATION OF REQUIRED CURRENT

Photon emission is a Poisson Process. The probability to see k photons from time t’=0 to t’=t is given by equation A1.1. P ( X t  k ) (  t ) ke ^  t / k! (A1.1) Lambda is the rate of photon emission. If lambda is a function of time the probability is given by equation A1.2.

   ^  t^  t t dt k P X t k 0 t dt e k 0 ( ) ( ) ( ( ) ) /!  

(A1.2)

The probability to see 0 photons up to time t is given by equation A1.3 which is equation A1.2 with k=0.     t t dt P X t e 0 ( ) ( 0 )  (A1.3) The probability to see 1 photon in a small interval of time is given by equation A1.4. t t t t t t t t^ dt t P X t t dt e t te     ^     

   ^  ()

( ) ( 1 ) ( ( ) ) ( )^     (A1.4) The right side of equation A1.4 is true assuming the time interval is very small so that lambda is constant over that time interval. The probability that 1 photon hits in a small time interval at time t and 0 photons hit before that time is given by equation A1.5.              t t dt t t dt t t P Xt P X t t te e t te 0 ( ) 0 ( ) ( 0 ) ( 1 ) () (^ ) ()      (A1.5) Where the right side of equation A1.5 is true assuming the time interval is much smaller than t. This quantity should be made to be constant by controlling lambda. Since our signal must repeat, the constant probability should be given by equation A1.6 where T is the period of the signal. P ( Xt  0 ) P ( X  t  1 ) t / T (A1.6) Equations A1.5 and A1.6 imply the equality given by equation A1.7. t e T t t dt ( )^01 / ( )     

(A1.7)

The solution to equation A1.7 is known to be given by equation A1.8 and is verified below.  ( t ) 1 /( T  t ) (A1.8) ( ) 1 /( ) ln( ) ln( ) ln(( )/ ) 0 0 t dt T t dt T t T T t T t t

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity counter_2 is Port ( clk : in std_logic; enable : in std_logic; asynch_clr : in std_logic; rec_bit : in std_logic; ack_bit : out std_logic; Q : out std_logic_vector(7 downto 0); L : out std_logic_vector(7 downto 0)); end counter_2; architecture Behavioral of counter_2 is signal count: std_logic_vector(7 downto 0); signal output: std_logic_vector(7 downto 0); signal hold_bit: std_logic; signal reset: std_logic; signal rec: std_logic; Begin process(clk, asynch_clr, rec_bit) begin rec <= rec_bit; if (asynch_clr='1') then count <= "00000000"; elsif (clk'event and clk='1') then if (enable='1') then count<=count+"00000001"; --count <= "10000000"; end if; end if; if (count = "00001001") then count <= "00000000"; reset <= '1'; else reset <= '0'; end if; if (reset = '1') then hold_bit <= '0'; end if;

if (rec = '1') then hold_bit <= '1'; end if; if (count = "00000000") then output <= "11001001"; elsif (count = "00000001") then --output <= "10101001"; output <= "11001010"; elsif (count = "00000010") then --output <= "10101010"; output <= "11001100"; elsif (count = "00000011") then --output <= "10101010"; output <= "11001101"; elsif (count = "00000100") then --output <= "10101010"; output <= "11001110"; elsif (count = "00000101") then --output <= "10101010"; output <= "11001111"; elsif (count = "00000110") then --output <= "10101011"; output <= "11010000"; elsif (count = "00000111") then --output <= "10101011"; output <= "11010001"; elsif (count = "00001000") then --output <= "10101011"; output <= "11010010"; else --(count <= "00001001") then --output <= "10101100"; output <= "11010011"; end if; --output <= "11111111"; if (hold_bit = '1') then output <= "00100000"; end if; end process; L <= count; Q <= output; ack_bit <= hold_bit; end Behavioral;