Operating Systems Exam: McKusick et al's File System Paper & Scheduler Algorithms, Exams of Operating Systems

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Operating Systems Comprehensive Exam

There are five questions on this exam. Please answer any four questions.

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1. The following questions pertain to McKusick et al's A Fast File System for UNIX paper. To get credit, you must answer all of them correctly. a. In 10 words or less, state the primary design principle promoted by this paper. b. Identify the two primary techniques used to promote reliability, and explain how they are used. c. What is the purpose of the bit map, and why was it chosen over a free list? d. Identify the two primary techniques used to promote performance, and explain how they are used. e. Identify the two primary sources of overhead, and the difficulties in trying to remove them.

In an effort to improve performance, the CEO has asked the programming team to try out a number of different scheduling algorithms. Rather than replace the current scheduler, however, they've heard a rumor that it is possible to reuse the current one and are hoping you can help. Your task is to replace the current job priorities with new positive integer priorities so that the current preemptive, priority scheduler will schedule them in a manner identical to a scheduling algorithm running the prescribed algorithm. Assume that you assign the priorities before the system starts running. For each specified algorithm, list the priorities you would use, as well as the new starting and ending time for each job. b. Round-Robin. c. First in, First out (FIFO). d. Shortest job first (SJF) ( not SRTF). e. If the company is concerned with minimizing the average completion time Tfinish − Tarrival and willing to ignore the initial priority assignments, which scheduling algorithm should they use?

3. A problem on concurrency. a. An operating system routine uses a simple binary search table that supports two concurrent asynchronous processes: Search and Update. Search repeatedly looks to see if various keys are in the table, and Update repeatedly inserts or removes various key in the table. Assume the table, which has many slots, initially contains three keys B, C, D in slots 1, 2, and 3 respectively. The Search process for finding B starts by doing a READ of the middle occupied slot 2; finding that C is greater than B, the Search process then does a READ of slot 1 where the key B is found. Suppose the Update process wishes to add a new key A concurrently. This process puts A in slot 1, B in slot 2, C in slot 3, and D in slot 4. We need to ensure that, despite the concurrent operation of the Update process, the Search process returns consistent (though possibly stale) results. We assume that each READ or WRITE to a memory slot is atomic; and, the system allows explicit Read and Write Locks. The standard solution to this concurrency problem is to use two copies of the table and move a pointer atomically to the updated table. Describe briefly the sequence of memory READS and WRITES required in the above example to do the Update and describe any locking needed to swing the pointer to the updated table.

4. Many processors provide intrinsic hardware support for operations that can read, modify and write one or more memory locations atomically (e.g., test-and-set, compare- and-exchange). These operations are, in turn, used for constructing higher-level synchronization primitives such as mutexes or semaphores. However, some architectures do not provide support for complex atomic operations. In other cases, the runtime overhead is too high to be efficient. In both cases, the operating system emulates them instead. A classic way to ensure such atomicity on a uniprocessor is to disable interrupts for the duration of the instruction sequence that must be atomic. For example, consider the compare and exchange operation that atomically compares the value stored at a given address with a value (v1) and if they are equal stores another value (v2) at the same address. The operating system can emulate this by disabling interrupts as follows: int cmpxchg(int addr, int v1, int v2) { int ret = 0; DISABLE_INTERRUPTS(); if (addr == v1) { *addr = v2; ret = 1; } ENABLE_INTERRUPTS(); return ret; } In this question we will consider an alternative implementation technique, called a Restartable Atomic Sequence (RAS). It works as follows: the instructions that are part of the RAS are registered with the kernel. When an interrupt happens, the PC of the interrupted thread is saved as usual. However, if the kernel does a context switch to another thread AND the saved PC was within a registered RAS region, then the saved PC is "rolled back" to the beginning of the RAS. This way, when the interrupted thread is rescheduled, the sequence of instructions will be re-executed from the beginning... hence the term restartable. Here is an implementation of compare-and-exchange using RAS: int cmpxchg(int addr, int v1, int v2) { int ret = 0; BEGIN_RAS if (addr == v1) { *addr = v2; END_RAS ret = 1; } return ret; }

a) Is this implementation of cmpxchng guaranteed to complete atomically on a uniprocessor? Why or why not? Be specific. b) Is this implementation of cmpxchng guaranteed to complete atomically on a shared memory multiprocessor? Why or why not? Be specific. c) RAS is an optimistic technique and can be considerably faster than other approaches (including intrinsic hardware support). Explain what makes it so fast and why it is an optimistic technique.