Quiz 10 Answer Key | Electronics | ECE 2204, Quizzes of Basic Electronics

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ECE 2204 Electronics Fall 2009 Quiz #10 November 18 (Wednesday) Weight: 10 points Name (PRINT): e ID# An optimal size inverter, in which both the rise and fall times are equal, has the following sizes. NMOS: Length (L) = Ly, Width (W) = Wy PMOS: L=Ly, W = 2W, where W, and L, are the unit length of the width and the length, respectively. 1. Consider the NOR gate given below for the following problems. a) We want to size the NOR gate to have the same fall and rise times of the optimal size inverter. Find the size of the MOS devices: AINMOS:L=__ | L, W=_i ow, war AIPMOS:L=__ | L, Ws 6 w, eft 000 edt b) The current input is ABC = +44, and it changes to — DF Se net Which input value gives the shortest . 4 Jee Jad ABC= | 4 4 CTLs my ., ni ge! 2. Which one takes up more silicon area between a 2-input optimal size NAND~gate and a 2- input optimal size NOR gate? 3. What is the other major impact of a large gate area on the performance in addition to high chip cost?