HDL Based Digital Design using Verilog: FPGA Implementation and Optimization, Slides of Data Communication Systems and Computer Networks

Download HDL Based Digital Design using Verilog: FPGA Implementation and Optimization and more Slides Data Communication Systems and Computer Networks in PDF only on Docsity!

SS-CARE School of Engineering Spring 2007

HDL Based Digital Design

Lecture 24

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

FPGA Based System Level Reuse Issues^ „

Synchronous vs. Asynchronous Design Style^ „

Avoid using latches „ Use D registers instead of latches „ Very few FPGA devices have latches available,therefore;

function of the latches can vary from one architecture to the next „ Synthesis tools for FPGAs do not process hold-time requirements because of the uncertainty ofrouting delays, it is not recommended toimplement latches with combinatorial feedbackloops

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering „^ Memory and Memory Interface

„^ Memory compilers developed for ASICs are not currentlydesigned to target FPGA architectures „^ FPGAs architectures can accommodate small to mediumblocks of memory on-chip „^ Distributed RAM can be used for status registers, indexregisters, counter storage, constant-coefficientmultipliers, shift registers, FIFO or LIFO etc „^

Dual port RAM simplifies the designs of FIFOs. „^ The capabilities of distributed blocks of memory arearchitecture dependent „^ Medium size memory can utilize block memory structuresof the FPGA architecture

FPGA Based System Level Reuse Issues

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Coding for FPGA „^ Course-grain FPGA architecture like Xilinx’sVirtex and Altera’s Apex are more sensitive tocoding styles and design practices than ASIC „^ A logic level in a FPGA is considered to be oneCombinatorial Logic Block (CLB) or LogicElement (LE) delay. „^ Each CLB has a given throughput delay and anassociated routing delay, once the amount oflogic that can fit into one CLB is exceeded,another level of logic delay is added. „^ FPGA architectures are register-rich. RTLcoding styles that utilize registers candramatically increase performance

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Coding for FPGA „^ Partitioning at Register Boundary

„^ For large blocks, both inputs and outputsshould be registered „^ For smaller modules, either the input or theoutput of the module should be registered „^ Registering both the input and output makestiming closures within each block completelylocal „^ Unlike ASICs, there is no need for buffers to beinserted at the top level to drive long wires „^ Defensive timing design is one way to assurethat timing problems will not limit use of themodule

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Coding for FPGA „^ One-Hot State Machines

„^ A good state-machine approach for FPGAslimits the amount of fan-in into one logic block „^ It is recommended to use a one-hot-encoding(OHE) style because of fan-in limitations of CLBand availability of large number of registers inFPGA „^ Binary encoded state sequences will have many,wide-input logic functions to interpret theinputs and decode the states, in a FPGA this canresult in several levels of logic between clockedges

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

Coding for FPGA „^ In Xilinx Virtex device, each CLB can implement any6-input function and some functions of up to 13variables. This means an 8-to-1 Mux can beimplemented in 1 CLB delay and 1 localinterconnect in 2.5ns (-6 device) „^ To avoid long path delays, do not use long Nestedif constructs „^ if-else constructs are much slower unless theintention is to build a priority encoder „^ Use case statement for complex decoding and usethe if statement for priority decoder design „^ Use multiplexer-based buses when designing forreuse

and use tri-state busses for one-time use only designs to get better timing optimization

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering Rows of programmablelogic building blocks

rows of interconnectAnti-fuse Technology:Program Once

8 input, single output combinational logic blocksFFs constructed from discrete cross coupled gates

Use Anti-fuses to buildup long wiring runs fromshort segments

I/O Buffers, Programming and Test Logic Logic Module

Wiring Tracks

I/O Buffers, Programming and Test Logic I/O Buffers, Programming and Test Logic

I/O Buffers, Programming and Test Logic

Actel Programmable Gate Arrayscourtesy Actel

HDL Based Digital Design using Verilog By M. Mohsin Rahmatullah @ SS-CARE School of Engineering

x^1 x^2 (a) Circuit for a two-input LUT

f

0/1 0/1 0/1 0/

00 01 10 11

1 0 0 1 xx^1 2 (b) f^ x^1

xx 1 2 1 x + 2 =

x^1 x^2 (c) Storage cell contents in the LUT

1 0 0 1

f^^1 f^^1