Ripple Carry Adders in Sequential Logic Design, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda
  1. MSI: Ripple Carry Adders
• Announcements
  1. HW# 9 assigned.

• Addition – Half Adder
  • one bit addition can be accomplished with an XOR gate (modulo sum 2)

0 1 0 1 +0 +0 +1 + 0 1 1 10

• notice that we need to also generate a “Carry Out” bit
• the “Carry Out” bit can be generated using an AND gate
• this type of circuit is called a “Half Adder”
• it is only “Half” because it doesn’t consider a “Carry In” bit

• Addition – Ripple Carry Adder
  • cascading Full Adders together will allow the Cout’s to propagate (or Ripple) through the circuit
  • this configuration is called a Ripple Carry Adder

• Addition – Ripple Carry Adder
  • What is the delay through the Full Adder?
    • Each Full Adder has the following logic:

Sum = A ⊕ B ⊕ Cin Cout = Cin∙A + A∙B + Cin∙B

• tFull-Adder will be the longest combinational logic delay path in the adder