ECE 2534 Interrupt Service Routine and Memory Interface Timing Inequalities, Exams of Microprocessors

Instructions for writing an interrupt service routine to track debounced 0-1 transitions on switches without using delay loops, and writes down the timing inequalities for specifications a, b, and c of the memory interface discussed in class.

Typology: Exams

Pre 2010

Uploaded on 05/14/2009

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ECE 2534 Test #2 April 24, 2009
1. You are to write an interrupt service routine that tracks debounced 0-1 transitions
on the switches in the GPIO_Switches register without using delay loops. You
may assume that the switches will settle within 1msec of their initial movement.
Every time a debounced 0-1 transition is detected you are to set the corresponding
bit in a global variable named CHANGES. You can assume that the main routine
has turned on GPIO interrupts from the switches. The following registers may be
useful:
INTC_ISR unused|switches|timer|
INTC_IER
INTC_IAR
GPIO_Switches unused|N|E|W|RA|RB|RC|S3|S2|S1|S0|
GPIO_Switches_TRI
GPIO_IER Switches is LSB
GPIO_ISR Toggle on writing 1
GPIO_GIE Enable is MSB
TLR0
TCR0
TCSR0
unused|ENALL|PWMA0|T0INT|ENT0|ENIT0|LOAD0|ARHT0|…
CAPT0|GENT0|UDT0|MDT0
2. For the memory interface we discussed in class, which is pictured in the attached
figure, write down the timing inequalities for the following specifications:
a. tDVEH
b. tWLEH
c. tAVEL
pf3
pf4
pf5

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ECE 2534 Test #2 April 24, 2009

  1. You are to write an interrupt service routine that tracks debounced 0-1 transitions on the switches in the GPIO_Switches register without using delay loops. You may assume that the switches will settle within 1msec of their initial movement. Every time a debounced 0-1 transition is detected you are to set the corresponding bit in a global variable named CHANGES. You can assume that the main routine has turned on GPIO interrupts from the switches. The following registers may be useful: INTC_ISR unused|switches|timer| INTC_IER INTC_IAR GPIO_Switches unused|N|E|W|RA|RB|RC|S3|S2|S1|S0| GPIO_Switches_TRI GPIO_IER Switches is LSB GPIO_ISR Toggle on writing 1 GPIO_GIE Enable is MSB TLR TCR TCSR unused|ENALL|PWMA0|T0INT|ENT0|ENIT0|LOAD0|ARHT0|… CAPT0|GENT0|UDT0|MDT
  2. For the memory interface we discussed in class, which is pictured in the attached figure, write down the timing inequalities for the following specifications: a. tDVEH b. tWLEH c. tAVEL