Senior Design Project Lab – Digital Audio Controller | ECE 445, Study Guides, Projects, Research of Electrical and Electronics Engineering

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Digital Audio Controller 2302 by Todd M. Konecny Insoo Shin Jay Burgett T.A.: Jeff Cook February 26, 2001 Project #

Abstract The Digital Audio Controller 2302 is an electronic signal processor that alters the frequency spectrum of a stereo audio program. The 2302 is a hybrid device that utilizes the precision of a digital signal processor for filtering and analog circuitry for real-time control of the gain of the individual filter outputs. This device is primarily used by nightclub disc jockeys to dramatically alter the overall response of the sound system during live performances. Signal integrity in the DAC 2302 is maintained due to strict distortion tolerances held over filter responses and analog amplifier stages. Using the industry standard sampling rate of 44.1kHz and digital filters designed to have less than 1% ripple as well as linear phase distortion results in non-audible distortion in the digital section. Carefully chosen op-amps and extremely low-tolerance analog devices in the analog circuitry allow for test results of a tenth of a dB in variation over a bandwidth much greater then the audio range. ii

1. INTRODUCTION

In the world of professional audio, products arise due to the imagination of artists. Many of these products use a combination of currently available devices in a new fashion. Equalizers, compressors, and noise-gates are examples of devices designed to be technical tools in the audio industry that have been taken out of the hands of the “engineer” and used for purposes other than those they were originally meant for. One such device that has recently become popular is the “active crossover.” Conventionally, an audio crossover is a network of filters used to divide the audio spectrum into frequency bands that are best suited to the different sized transducers used in the sound system. The points at which these bands are divided (“crossover points”), the types of filters used, their delay, and their gain is individually adjustable to achieve a “flat” system. The unit that performs these functions is a “system controller” and is usually a set-and-forget type device that is not altered on a normal basis. This concept has been converted by dance-club DJ’s into the “active crossover,” essentially a system controller that can be continually altered by the performer. An active crossover divides a stereo program into bands, controls the gains of these bands, and recombines them into a stereo program. The active crossover is not used as the main system controller, but is instead used as a conventional equalizer would be. The difference between the two being that a one-third octave graphic equalizer has 15 dB^ of boost or cut in 31 bands, while the active crossover has three bands with complete attenuation or 3 dB boost and only three knobs. Thus the active crossover has the potential to be a simple interface with more spectrum control than an equalizer. Most current incarnations of the active crossover add distortion to the program that compromises the quality of the sound system. Since these systems operate at sound pressure levels of 115 dB , distortion is readily apparent and the fidelity of each electronic component in the signal chain becomes crucial to overall system quality. It is for this reason that we chose to design the Digital Audio Controller 2302. The ‘2302’ indicates that the device accepts a stereo program as input (2), internally divides the program into three bands (3), has no bands of EQ (0), and has a stereo output (2). A general block diagram of the device is shown in Fig.1.1.1. (All figures at end of report) The Digital Audio Controller 2302 uses digital filtering combined with extremely high tolerance/low noise analog circuitry to present a device that allows for the spectral manipulation of a stereo audio program in real time with a simple control interface. The design of the 2302 was divided into three major parts: software design (DSP coding), hardware design (analog circuitry), and testing. The software coding took the least amount of time due to the use of Matlab to design and graph the filter responses. The analog design was difficult in that there are many devices that can be chosen and each has unique advantages. Testing entailed making sure that the unit worked and then running various tests for magnitude response and any distortion effects that might be present. All of these are detailed later in the paper.

2. DESIGN PROCEDURE

The priority in the design of the Digital Audio Controller 2302 is to add as little distortion to the signal as possible. This is to make the device compatible with sound systems of the highest quality. Many system engineers will not include a piece of audio equipment in a system design, even if their client specifies it, if it degrades the quality of their system. Fortunately, cost is seldom an issue in these circumstances, and thus most decisions made in the design of this device are quality-based with cost becoming a second consideration. 2.1 Software Digital filters were chosen over analog because of the accuracy with which the filter response can be created. The use of a digital signal processor for filtering allows for completely definable filter responses that do not suffer the limitations of component tolerances and thermal noise that analog devices do. Analog filters are prone to drift and inaccuracies that, given that the filter outputs are to be recombined, would be extremely noticeable in this situation. The software creates filters that have linear phase characteristics and ripple in the pass band of no more then 1%, which is inaudible to humans. The filtering imparts an overall delay on the program, but does not cause phase distortion among the individual bands. A DSP also has the advantage of upgrade-ability, should the need arise. Finite Impulse Response (FIR) filters are selected for the filtering because they have only linear phase shift within the pass-band [1]. FIR filters consist of multiplying the present sample and some number of previous samples with a list of coefficients and summing all of these results. This is in contrast to IIR filters, in which the input samples and previous output samples are used to calculate the present output sample. Infinite Impulse Response (IIR) filters would require less coefficients than FIR for the same filter slopes, but IIR filters have various drawbacks that make them an inferior choice to FIR filters for this design. The main drawback to IIR filters is that they impart a non-linear phase shift to the program [1]. This manifests itself as noticeable phase distortion in the pass band of the processed signal. Another drawback that occurs with IIR filters is the perpetuation of errors in the output signal. Since the output is calculated using previous outputs, error that is caused by electronic glitches or random circuit noise is in effect fed back into the system and maintained for a greater number of outputs then the single instant that it occurred. Any error in FIR filter output exists only for the time period that it is caused directly. Code Composer Studio was used extensively to troubleshoot the assembled code. It’s facilities for stepping through lines of code and displaying register values is invaluable to getting DSP code to function properly. 2.2 Hardware The analog portion of the device accomplishes several tasks. The circuitry outputs VU values to an LED bar graph, converts a differential input to single-ended,

3. DESIGN DETAILS

3.1 Digital Filter Design Computation of filter coefficients is done using Matlab, as it has many facilities that are very useful in designing filters. In order to design the exact responses given by the device specifications the command FIRLS is used. In this command, the number of coefficients, the start and stop points of the stop, pass, and transition bands as well as the sampling frequency are all entered as a single line of code. An example would be: hp = firls(len,[0,2,2,4,4,22.050]/22.050,[0,0,0,1,1,1]). Matlab’s response is to create a list of coefficients that can be used in a filter with the desired response. For this line of code the output filter would consist of a high-pass filter with a stop-band from 0 Hz to 2 kHz , a transition band from 2 kHz to 4 kHz , and a pass band from 4 kHz to 22. 05 kHz using len number of coefficients. These coefficients are then stored to an output file, which is loaded into the DSP within the code. Matlab is also used extensively to view the predicted response of the designed filters. The scripts that are used to create the filter coefficients automatically plot the response of the filters based on the computations. The plot of each filter magnitude can then be used to determine that the magnitude response ripple of each filter is restrained to 1% of total voltage. This involves increasing the number of coefficients given in the FIRLS command until the ripple is less than 1% of the average pass band value. An example of a filter magnitude response is shown in Fig. 3.1.1. The maximum number of coefficients is governed by the fact that all the filters must run within one sample period in order to have samples calculated and ready for output. 3.2 DSP Code Design The digital processing is done using a Texas Instruments TMS320C549 digital signal processor mounted on a Spectrum Digital TMS320LC54x evaluation board. This board has two analog inputs and six analog outputs, which is appropriate for this design. The board operates at a sampling frequency of 44. 1 kHz and has a clock speed of 80 MHz. This sampling frequency allows for a Nyquist frequency of 22. 05 kHz , which is appropriate for audio applications. Every filter within the code is performed using the mac command. An example of this command would be: mac AR2+0%,AR3+0%,A. This line of code takes the sample that AR2 is pointing at, which would be the oldest sample, and the address that AR3 is pointing at, which is the first of the filter coefficients, multiplies them and adds the result to the value in accumulator A. A is cleared previous to the mac instruction. Also previous to the mac command is a repeat command, which causes the pointers to traverse both the filter coefficients and the sample buffer and repeats the mac instruction. This accomplishes the summation of the products of the coefficients and samples. This line of code is used throughout the program and the

pointer values for AR2 and AR3 are updated each time. The resulting pointer values are also re-stored to be ready for the next time that filter is processed. The program begins by loading the core code. The core code initializes the DSP for processing by enabling the fractional arithmetic mode for the ALU and setting the clock speed to 80 MHz. The core code also serves to read and write input and output data in blocks of 64 samples. This code is pre-written and available from the ece archives. The code then creates variables that are used throughout the program for changing constants. For example, the variable FIR_len is the length of the number of FIR coefficients. Since several memory buffer lengths and the circular buffer length are determined by this value, it is advantageous to make those lengths dependent on the value of a variable FIR_len instead of actual numerical values in the code. Other variables are also created for the same purpose. The code also creates several memory locations to store input samples, output samples and the coefficients of the FIR filters. Since several filter outputs are inputs to other filters, it becomes necessary to store these outputs somewhere, since they cannot be left in the accumulators. This is done using the memory locations created at this point. Some examples are rhiout , rmidout , and rloout , the names of which are indicative of the filter output that is stored in each variable. Since the analog-to-digital converters operate at 44. 1 kHz , the Nyquist frequency becomes half of that: 22. 05 kHz [1] This means that the input signal to the ADC’s cannot contain any frequencies greater than 22. 05 kHz or aliasing will occur. The error from aliasing will begin in the high frequency area. The evaluation board contains analog filters that are meant to prevent this aliasing, but the filters allow some frequencies above 22. 05 kHz to enter the analog-to-digital converters. Examination of the output of the board at frequencies above 22. 05 kHz shows that aliasing occurs in spite of the on-board anti-aliasing filters. Thus the code begins with a low-pass filter that, although termed an anti-aliasing filter in the code, in actuality filters out the aliasing that has already occurred. This filter is a low-pass filter with a pass-band from 0 Hz to 18 kHz. The output from this first filter is used as the input for two filters that accomplish the first true band division. A high-pass filter creates the high band with a pass-band starting at 4 kHz^ and a low-pass filter creates the beginning of the mid and low-bands with a pass-band that stops at 4 kHz^. These filters are symmetric with the result that their addition will result in a completely flat output. Since the transition bands of the filters overlap, when bands are recombined the transition bands will add. Thus the bands should have values that, when added, result in the original signal level. Placing the 6 dB^ -down points of each band at the same frequency (i.e. make them symmetric) is equivalent to having the bands at half the original signal’s level at the same frequency. Then the addition of this frequency results in a gain of 0 dB , or no change in signal level.

to this problem, as well as its overall versatility. Each channel of the bar graph consists of six green LED’s to represent the safe region, two yellow LED’s to warn of the upcoming overload region, and two red LED’s to represent overload, or clipping, of the input signal. The voltage reference point is determined by sending a sine wave of known voltage through the DSP and the bar graph. The output waveform from the DSP is monitored on an oscilloscope. Once the scope shows that the DSP begins to clip the sine wave, the trim pots of the bar graph are adjusted to display in the red region for this voltage level. 3.4 Analog Input Stage The input stage of the 2302 is designed to be compatible with professional audio industry standards for interconnection. The standard interconnect line contains three conductors carrying signal in-phase, signal out-of-phase, and a grounded shield. This in- phase and out-of-phase characteristic creates a differential signal on the line, which is converted to single-ended by the input stage (Figure 3.4.1). Differential lines are referred to as “balanced” in the audio industry. The signal is differential in order to deal with line noise in the following manner. Any RF or random noise incident upon the line appears on both the inverted signal- carrying and non-inverted signal-carrying conductors and thus becomes a common mode between the two. The input stage of the 2302 is differential in nature and amplifies only those signals that are not common to both of its inputs, here, pins 2 and 3. In this manner the signal, which is 180 degrees out-of-phase across the two inputs, is amplified and the noise, which is a common mode voltage, is attenuated [2]. The effectiveness of this operation depends greatly on two factors: the ability of the op-amp to reject common mode voltages and the precision of the passive components used on the input and feedback circuitry. The National Semiconductor LM318 is a precision, low-noise operational amplifier that has a typical CMRR of 100 dB , compared to a value of 80 ^90 dB for the LM709, an industry standard operational amplifier, and is thus chosen for this design. The LM318 is also an extremely fast device with a slew rate of 70 V^ /^  s , compared to a typical value of 20 V^ /^  s. This reduces transient distortion at the output of the op-amp. The precision of the passive resistors are crucial in the differential design because any components that affect the input signal preceding the differential input stage have the potential of reducing the equality of the two common mode noise components. This creates a noise component that is not common mode, which is then output from the op- amp. 0.1% tolerance resistors are used on the input stage to ensure that the signals input to the LM318 are as close to identical as possible. Ideally, the input/output gain of a device such as the 2302 that is not intentionally used to alter the level of the program should be equal to unity. This is because amplifiers are the most accurate when they are not altering the gain at all. Overall program gain

changes are made at a single stage somewhere early in the signal chain (e.g. the mixing console) and all devices downstream of that amplifying unit operate at unity gain. Thus each op-amp stage’s gain of the 2302 (excepting the gain stage in which the gain of the program is intentionally changed) will be unity, or slightly larger to account for losses. Sedra and Smith [3] state that the gain of an operational amplifier is dependent on the values of the input and feedback resistance in the relation: 2 3 R

R

v v I

O 

As shown in Figure 3.4.1, the input resistance of the input stage is R 2^ (and R 1^ ), which is equal to 6.^04 k . The value 6.^04 k is chosen in order to provide high input impedance for the standard 600  audio line to minimize the amount of current the device draws from the line, while providing enough current to create a good signal signal-to-noise ratio in the op-amp via it’s feedback resistor. The “unity gain” factor of this stage is not unity gain per each conductor, as each conductor has a full-scale signal on it. The gain in decibels is found as: voltage gain in decibels = I O v v 20 log 10 , (2) where vO^ is the output voltage and v^ I is the input voltage [3]. If both signals were un- attenuated and the inverted signal were inverted and added to the non-inverted signal, the output of the op-amp would be double the input, for a gain of 6 dB^. In this case the values would be: vO  v (^) inverting  vnon  inverting , keeping in mind that the non-inverting voltage is identical to the inverting voltage except for being 180 degrees out of phase. Thus their subtraction results in the summation of their voltages. Substituting this expression for vO^ gives the voltage gain as dB v v v v v I I I 20 log inverting^ non^ inverting 20 log^26. 02 10  10   (^)  . For this reason, in the differential amplifying circuit, each signal’s gain must be halved and then added to achieve true unity gain. This is accomplished by making the gain for each of the two signals equal to 0.5 or –6dB. Then

The gain stage shown in Figure 3.5.1 operates on the simple principal that the gain of an operational amplifier is determined by its feedback resistance value divided by its input resistance value ( see Equation (1)). By placing a potentiometer in series with the input resistor the gain of the op-amp is controlled by varying the value of the input resistance value. The top of the potentiometer is attached to the output of the 100  resistor, which is the output of the input stage. The wiper of the potentiometer is taken as output and is connected to the 20 k^ resistor, which forms the input resistance of the gain stage. The bottom of the potentiometer is connected to ground. The specifications of the 2302 state that the user is to have the ability to add about

2. 5 dB of gain to any frequency band. This gain is determined by the ratio of feedback resistance to input resistance of the gain stage’s op-amp: 6 7
3. 5 20 log (^10) R R dB   Then, rearranging terms to find R 6^ yields 20
4. 5

7 6

R

R  (4)

Thus the value of R 6^ is dependent on the value of R 7^ , which in turn is dependent on two things: desired current through the feedback loop and the 3 dB^ down point of the high-frequency compensation filter. Since the feedback resistor drains some finite amount of current from the op-amp output its resistance value should be moderately high in order to not attenuate the output value by a great amount, but not too high so as to cause noise to be amplified due to low current in the feedback resistor. Choosing R 7^ to be 26.^7 k  causes the current drained from the output to be slightly less than a third of the output, since this resistance is in parallel with the input resistance of the summing stage, which is 10 k . This is a good trade off as most of the current is then sent “down stream” to the rest of the circuit, while a sufficient amount of current is produced in the feedback resistor to drive the op-amp in a quiet manner. This value for R 7^ in turn defines the value of the feedback capacitor of the low pass filter. Restricting fo^ to be at least a power of ten above the maximum signal frequency of 20 kHz^ , a capacitor value of 30 pF results in a 3 dB^ down point of 198 , 695 Hz. Given R 7 to be 26.7k then defines R 6 , from Equation (4), to be:

20 6 2.^5

k

R .

Thus the ratio of R 7^ to R 6^ allows for the 2. 5 dB boost in gain when the pot is all the way on.

If the potentiometer is fully clockwise, which it is when the 2. 5 dB boost is enabled, its input is shorted to its wiper/output and becomes a 50 k resistance to ground and the circuit is that of Figure 3.5.2. This circuit has a gain that is not exactly equal to the gain of the actual op-amp due to the 50 k  resistance to ground. The voltage gain between V 01^ and VZ^ can be determined in the following manner from Munson [5]. Referencing Fig. 3.5.2, the voltage at node V 01^ is the voltage output from the input stage LM318. Then

 

100 14 ,^385.^7

01 1 20 1 50 1 01 1

V V

i

k k

since the 50 k resistor and the 20 k resistor are in parallel and both go to ground. Then ( )( 1 0. 00695 ) ( 0. 993 )( ) 14 , 385. 7 ( )( 100 ) 01 (^1 )(^100 ) 01 01 V 01 V 01 V Vx V i V          . The current i 2^ is then found from ( 4. 95 10 )( ) 20 ( 0. 993 )( ) 20 20 01 01 5 2 V k V k V k V V i x x y           The voltage V^ z at the output of the op-amp is then Vz ( 26. 7 k )( i 2 )( 26. 7 k )( 4. 95  10 ^5 )( V 01 )( 1. 3257 )( V 01 ), and the voltage gain is dB V Vz 20 log 20 log 10 ( 1. 3257 ) 2. 449 01

10 ^ .

This is the gain between the output of the input stage and the output of the gain stage. For the situation when the pot is all the way counter-clockwise, the gain remains

2. 5 dB , as the input resistance has not changed, but the input voltage is now zero as it is shorted to ground. Thus v^ I ^0. Now, since there is no current through the 20 k input resistor, there is no current through the feedback resistor and vO  (^0). The output voltage gain becomes undefined v v I O (^)   0 0 20 log 10 20 log 10

positive and negative polarities, presented to the input of the op-amp. The second waveform is the output of the servo. The third waveform shows that the output of the gain stage op-amp remains stable at 0 V^ dc even though it has as its input the DC voltage. Fig. 3.5.4 illustrates the servo circuit that gives rise to the waveforms. 3.6 Analog Muting Stage The muting circuitry of the 2302 is based around three switches, high sensitivity coil relays, and AND gates and is shown in Fig. 3.6.1. The AND gate controls a MOSFET, which is between the relay and ground. If the output of the AND gate is low, the MOSFET is in cutoff and isolates the relay control from ground. This causes the relay to be open. Since the signal is connected to the closed-circuit terminals, this corresponds to the muted situation. If the output of the AND gate becomes high, the MOSFET changes to the active state, creating a path from the relay to ground, which puts a potential of  5 V across the control pins of the relay. This causes the relay to activate (close), making the signal path and effectively un-muting the circuit. One of the AND^ gate inputs is connected to the output of the TL7705A. This IC outputs a logic one when its sense input is low. This input is connected to ^ Vcc through a 47 ^ F capacitor. Upon power up, this capacitor, being uncharged, connects the control input to ^ Vcc , sending a logic zero to the AND gate that in turn forces the MOSFET to be in cutoff. This has the consequence of muting the channels regardless of the positions of the actual mute switches. Eventually the capacitor will become fully charged and present a logic low voltage to the control input of the IC, which in turn will output a logic one to the AND^ gate. Assuming that the mute switches are off (un-muted and presenting a logic one to the other AND input), this un-mutes the channels. In this fashion, the unit is temporarily muted during power-up to allow the circuitry to stabilize. The other input of the AND^ gate is connected through a Schmitt trigger inverter and switch to ^ Vcc. The inverter is necessary because it is desired to present a logic one to the AND^ gate when the switch is off. A 10 k^ pull down resistor guarantees that a logic zero is present at the input of the inverter if the switch is off, which in turn presents a logic one to the AND gate. When the switch is closed (muted position), it shorts  V cc to the input of the inverter, which presents a logic zero to the gate of the MOSFET, which then causes the relay to open and mutes the channels corresponding to that button. The mute LED’s are actuated by placing their anode at ^ Vcc and their cathode at the output of the AND^ gate. Thus, when the channels are not muted, the output of the AND gate is high and there is no voltage across the LED. When the channel is muted, the output of the AND gate goes to zero and the LED has ^ Vcc across it, causing it to light. 3.7 Analog Summing Stage

Another specification of the 2302 is that it must sum the three frequency bands (low, mid, and high) to produce a pair of full spectrum outputs. As shown in Fig. 3.7.1, the circuit configuration for this stage is a weighted summer that sums the three signals coming from the gain stage [5]. Each output of the gain stage is connected to a resistor of the same value as R 11^ , which is 243 . Thus, when added in series with R 12^ ,^ R 13 , or R 14^ , each being

9. 76 k , the total series resistance, R^ s , is 10 k . The outputs of the gain stages, low, mid, and high, are applied to Rs^ , which in turn is connected to the inverting terminal of the LM318. Since the positive terminal is connected to ground, the LM318 will have a virtual ground appearing at its negative terminal. Ohm’s law then gives us the currents: s low low R v i  (^) , s mid mid R v i  (^) , s high high R v i  (^) (7) All currents sum together to produce the current i : i = ilow^ + i^ mid + i^ high (8) This current will be forced through the feedback resistance^ R 15^. Thus, the output voltage of the summing stage is, v (^) 0  0  iR 15. Then low mid high^  s high s mid s low s o v v v R

R

v R

R

v R

R

v R

R

v  ( 15 ^1515 )^15 (  . (9) That is, the output voltage is the weighted sum of the input signals low, mid, and high. Solving for the gain of the op amp, low mid high s o sum R R v v v v A  ^15  

Since the desired gain from the summing stage is unity, values for the resistances R 15 and R^ s are chosen to be 10 k^ . This value is appropriate because it does not load the summing stage op-amp. The capacitor is added in parallel to the feedback resistor to control the bandwidth and reduce noise feeding into the circuit as mentioned earlier. By adding a capacitor in parallel to R 15^ a 3dB frequency of 3. 18 MHz is produced, which is above the maximum operating frequency of 20 kHz.

which, in dB is dB v v in out 20 log 10  2  3. (^5). The phase difference between the outputs of the two op-amps is    vout 2 (^)   vout  180 . (11) This produces the differential output required in the original design specifications.

4. DESIGN VERIFICATION

4.1 Hardware Verification Each sub-circuit and the entire circuit were constructed and simulated in PSPICE to check for frequency response. This was a preliminary check on calculations and circuit responses. All calculated responses were shown to be accurate and the actual physical circuit was constructed in order to determine actual current consumption, action of the potentiometers and to test the logic of the muting circuitry. In order to verify that the circuit design and implementation performs according to PSPICE predictions, test measurements were taken using an Agilent vector spectrum analyzer. On each of the inputs a frequency sweep was setup and the output of each of the 16 op-amps were viewed on the screen of the vector spectrum analyzer. In order to present the data that was observed on the screen, several discrete measurements were recorded. The output voltage measurement from every stage (input, gain, summing, and output) of the circuit was then placed in a table, which can be viewed on Table 4.1.1 (All tables at end of report). Since only one input signal was generated at a time, average values on the outputs were calculated. The gain from the input stage is very close to 0 dB , since this was the design specification. All other stages performed exactly to design specification, and the LEFT and RIGHT gains were very consistent. Less than tenth of a dB variation was observed throughout the entire circuit. 4.2 Software Verification The digital section of this design was tested for frequency response using a signal generator and oscilloscope. A sine wave generated by the frequency generator was applied to the input of each op-amp circuit while simultaneously being monitored on the scope. This made it possible to determine the magnitude response of each stage. The phase was checked by mathematically subtracting the outputs from the high bands and the low bands. The resultant waveform viewed on the scope had no variation as the test signal was swept through the transition bands. This shows that in the frequency ranges that are common to two bands, the phase response remains coherent.