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Sequential Logic II-Digital System Design-Lab Mannual, Exercises of Digital Systems Design

Baddi University of Emerging Sciences and TechnologiesDigital Systems Design

This file contains information about lab of Digital System Design. It was provided by Prof. Reshmi Jaiteley at Baddi University of Emerging Sciences and Technologies. Its helpful to computer science as well as students of Engineering. It includes: Arranged, Slot, LTI, Impulse, Interconncection, Correlation, Shifted, Impulse, Represented, Systems

Typology: Exercises

2011/2012

Uploaded on 07/26/2012

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1. Objective
After completion of this lab you will be able to
• Implement and simulate the sequential logic.
• Use of behavior logic statements in practical examples.
• Use of timing diagram.
2. Experiment
2.1 Design Statement
You are required to design and implement a state machine of a sequence
recognizer and then write a stimulus of it using ModelSim software. The correct
sequence is 1010. If the sequence is matched then it should lit a green led and
move to halt state and if the sequence is mismatched then it should lit a red led
and move in a halt state. It should only move from the halt state if the system is
reset.
Marking criteria
• Draw the state diagram.
• Implement and simulate state machine.
NOTE: Implement the above mention design using data flow and behavior modeling
only. You can design block with any of above mention construct but be sure to use both
type of construct.
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1. Objective

After completion of this lab you will be able to

  • Implement and simulate the sequential logic.
  • Use of behavior logic statements in practical examples.
  • Use of timing diagram.

2. Experiment

2.1 Design Statement

You are required to design and implement a state machine of a sequence recognizer and then write a stimulus of it using ModelSim software. The correct sequence is 1010. If the sequence is matched then it should lit a green led and move to halt state and if the sequence is mismatched then it should lit a red led and move in a halt state. It should only move from the halt state if the system is reset.

Marking criteria

  • Draw the state diagram.
  • Implement and simulate state machine.

NOTE: Implement the above mention design using data flow and behavior modeling only. You can design block with any of above mention construct but be sure to use both type of construct.

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