February 24, 2010 page 1 S. Derenzo
Solutions for Midterm #1 - EECS 145M Spring 2010
1.1 Edge-triggered D-type flip-flop:
one digital data input
one digital clock input
one digital data output
on every rising edge of the clock the output is set equal to the input
otherwise the output is held constant
1.2 Transparent latch:
one digital data input
one digital gate input
one digital data output
when the gate signal is high the output is equal to the input
when the gate signal is low the output is held constant
1.3 Tri-state buffer
one digital data input
one digital “output enable” input
one digital data output
when the “output enable” signal is high the output is equal to the input
when the “output enable” signal is low the output neither drives nor loads anything it is
connected to (high impedance state)
1.4 Set-reset latch
one digital “set” input
one digital “reset” input
one digital output that is “set” and “reset” by the two inputs
2.1
Elements needed for full credit
• 8 separate lines from output port to trigger inputs of the 8 digital devices
• eight separate set-reset latches with each “set” connected to the “data available (pulse)”
from the corresponding digital device
no points off for eight one-shots set for an output pulse width several times 1 µs. This would
work, but only if the computer reads the input port in a tight loop. It would not work if the
computer were multi tasking and was not able to read the input port frequently enough.
[5 points off if no set-reset latches to convert the very brief data available pulse into a
persistent signal that the computer can read and reset]
