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4 problems, 5 pages Exam Two Solutions 8 March 2012 Problem 1 (4 parts, 22 points) Building Blocks Part A (6 points) Implement a 2 to 4 decoder with basic gates. Part B (8 points) Suppose the circuit below has the following input priority: I 0 > I 2 > I 3 > I 1. Complete the truth table by filling in the input values that would produce the given outputs and derive a simplified expression for O 1. I 3
I 2
I 1
I 0
O 1
O 0
I 3 I 2 I 1 I 0 V O 1 O 0 0 0 0 0 0 X X x x x 1 1 0 0 0 0 1 0 1 0 1 x 1 x 0 1 1 0 1 0 x 0 1 1 1 O 1 = I^ 0 ⋅(^ I^ 2 + I^ 3 ) Part C (4 points) Which basic gate, having inputs X and Y, does the following circuit implement? Hint: Complete the truth table at the right. X Y Out (^0 0) 1 (^0 1) 0 (^1 0) 0 (^1 1) 0 This implements a NOR. Part D (4 points) If the mux in Part C is implemented with pass gates and inverters, does the implementation of the basic gate in Part C require fewer transistors than the gate's standard switch-level implementation? Circle one: **No Support your answer by giving the transistor count for each:
transistors in MUX implementation: 16 # transistors in switch-level implementation: 4**
4 problems, 5 pages Exam Two Solutions 8 March 2012 Problem 2 (3 parts, 24 points) Number Systems Part A (10 points) Convert the following notations: binary notation decimal notation 1100 0101. 197 10101.101 21. 1 1001.011 25. hexadecimal notation octal notation 0x1EC.58 754. D5.A 325. Part B (8 points) For the 12 bit representations below, determine the most positive value and the step size (difference between sequential values). Express all answers in decimal notation. Fractions (e.g., 3/16ths) may be used. Signed representations are two’s complement. representation most positive value step size unsigned integer (12 bits). (0 bits)
4K-1=4095 1
signed fixed-point (7 bits). (5 bits)
signed integer (12 bits). (0 bits)
2K-1=2047 1
signed fixed-point (9 bits). (3 bits) 256-1/8^ 1/ Part C (6 points) A 16 bit floating point representation has a 10 bit mantissa field, a 5 bit exponent field, and one sign bit.
What is the largest value that can be represented (closest to infinity)? 2 ___^15 ______
What is the smallest value that can be represented (closest to zero)? 2 ___-16______
How many decimal significant figures are supported? __ 3 ______
4 problems, 5 pages Exam Two Solutions 8 March 2012 Problem 4 (4 parts, 26 points) Registers and Latches Part A (8 points) Implement a transparent latch using only NOR gates, AND gates, and inverters. Label the inputs In and En , and output Out. Do not attempt to employ mixed logic notation. Also complete the truth table. In En Out A 0 Q 0 A 1 A Part B (7 points) Assume the following signals are applied to a transparent latch. Draw the output signal Out. Assume Out is initially zero. Part C (4 points) Consider a register with a selectable write enable (WE) and read enable (RE), implemented as shown below. Describe its behavior by completing the output values. Recall that the CLK signal indicates a full Φ 1 Φ 2 cycle; so the output should be the value at the end of a cycle (with the given inputs). Also indicate when a write and/or a read is being performed. IN WE RE CLK OUT W? R?
A 0 0 ↑↓ Z 0 N N
A 1 0 ↑↓ Z 0 Y N
A 0 1 ↑↓ Q 0 N Y
A 1 1 ↑↓ A Y Y
Part D (7 points) Assume the following signals are applied to a register with write enable. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out is initially zero.
