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EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 1
EE
Lecture 16
- D/A Converters (continued)
- DAC reconstruction filter
- ADC Converters
- Sampling
- Sampling switch considerations
- Thermal noise due to switch resistance
- Clock jitter related non-idealities
- Sampling switch bandwidth limitations
- Switch conductance non-linearity induced distortion
- Sampling switch conductance dependence on input voltage
- Clock voltage boosters
- Sampling switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters- DAC Design © 2010 Page 2
Summary Last Lecture
- D/A converters
- Practical aspects of current-switched DACs
(continued)
- Segmented current-switched DACs
- DAC dynamic non-idealities
- DAC design considerations
- Self calibration techniques
- Current copiers
- Dynamic element matching
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 3
DAC In the Big Picture
DACs
- Convert the incoming digital signal to analog
- DAC output staircase form
- Some applications
require filtering (smoothing) of DAC
output
Reconstruction
filter
Post processing^ Analog
Conversion^ D/A
DSP
Conversion^ A/D
Preprocessing^ Analog
Analog Input
Analog Output
...001...^000 110
Anti-Aliasing Filter Sampling +Quantization
"Bits to Staircase" Reconstruction Filter
DAC Reconstruction Filter
- Need for and requirements depend on application
- Tasks:
- Correct for sinc droop
- Remove “aliases”
(stair-case approximation)
B fs/
0 0.5 1 1.5 2 2.5 3 x 10^6
0
1
DAC Input
0 0.5 1 1.5 2 2.5 3 x 10^6
0
1 sinc
(^00) 0.5 1 1.5 2 2.5 3
1
DAC Output Normalized Frequency f/fs
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 7
Summary
D/A Converter
- D/A architecture
- Unit element – complexity proportional to 2B- excellent DNL
- Binary weighted- complexity proportional to B- poor DNL
- Segmented- unit element MSB(B 1 )+ binary weighted LSB(B 2 ) Complexity proportional ((2B1-1) + B 2 ) - DNL compromise between the two
- Static performance
- Dynamic performance
- DAC improvement techniques
- Symmetrical switching rather than sequential switching
- Current source self calibration
- Dynamic element matching
- Depending on the application, reconstruction filter may be needed
What Next?
- ADC Converters:
- Need to build circuits that "sample“
- Need to build circuits for amplitude quantization Post processing^ Analog
Conversion^ D/A
DSP
Conversion^ A/D
Preprocessing^ Analog
Analog Input
Analog Output
...001...^000 110
Anti-Aliasing Filter Sampling +Quantization
"Bits to Staircase" Reconstruction Filter
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 9
Analog-to-Digital Converters
- Two categories:
- Nyquist rate ADCs fsigmax^ ~ 0.5xfsampling
- Maximum achievable signal bandwidth higher compared
to oversampled type
- Resolution limited to <14bits
- Oversampled ADCs fsigmax^ << 0.5xfsampling
- Maximum achievable signal bandwidth significantly lower
compared to nyquist
- Maximum achievable resolution high (18 to 20bits!)
MOS Sampling Circuits
EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 13
Ideal T/H Sampling
Continuous Time
T/H signal (Sampled-Data Signal) Clock
Discrete-Time Signal
time
Track^ Hold
Practical Sampling Issues
vIN vOUT C
M
- Switch induced noise due to M1 finite channel resistance
- Clock jitter (edge variation of 1 )
- Finite Rsw limited bandwidth finite acquisition time
- Rsw = f(Vin) distortion
- Switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 15
Sampling Circuit kT/C Noise
- Switch resistance & sampling capacitor form a low-pass filter
- Noise associated with the switch resistance results in Total noise
variance= kT/C @ the output (see noise analysis in Lecture 1)
- In high resolution ADCs with such sampling circuit right at the input,
kT/C noise at times dominates overall minimum signal handling
capability (power dissipation considerations).
vIN (^) v OUT
C
R S
vIN vOUT
C
M
1 4kTR D f
Sampling Network kT/C Noise
For ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal or at times slightly larger compared to quantization noise: Assumption: Nyquist rate ADC
2
2
2
2
2
ChooseCsuch thatthermalnoiselevelisless(orequal)thanQnoise
ForaNyquistrateADC:Totalquantizationnoisepower 12
FS
B B
FS
B B
B
C kT V
C kT V
C
kT
^
D
D
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 19
Clock Jitter
- So far : clock signal controls sampling instants – which we assumed to be precisely equi-distant in time (period T)
- Real clock generator some level of variability
- Variability in T causes errors
- "Aperture Uncertainty" or "Aperture Jitter“
- What is the effect of clock jitter on ADC performance?
Clock Jitter
• Sampling jitter
adds an error
voltage
proportional to the
product of (tJ-t 0 )
and the derivative
of the input signal
at the sampling
instant
nominal (ideal)
sampling
time t 0
actual
sampling
time tJ
x(t)
x’(t 0 )
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 21
Clock Jitter
• The error voltage is
nominal
sampling
time t 0
actual
sampling
time tJ
x(t)
x’(t 0 )
e = x’(t 0 )(tJ – t 0 )
error
• Does jitter matter
when sampling dc
signals ( x’ (t 0 )=0 )?
Effect of Clock Jitter on Sampling of a
Sinusoidal Signal
Sinusoidal input Worst case
# of Bits fs dt << 12 16 12
1 MHz 20 MHz 1000 MHz
78 ps 0.24 ps 0.07 ps
FS (^) x s
B 1FS
B (^) s
A A 2 f^ f 2 e( t ) A 2 2 dt 1 2 p f
D
x x x x max x
max x
Fre que nc y :^ Amplitude :^ Af J itte r: dt x( t ) Asin 2 f t x'( t ) 2 f Ac os 2 f t x'( t ) 2 f A The n: e( t ) x'( t ) dt e( t ) 2 f Adt
p p p p
p
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 25
Statistical Jitter Analysis
p
p
p
x
x
x
f
f
f A
DR A
20 log 2
10
2 22
2 2 22
2 jitter
EECS 247 Lecture 15: Data Converters- DAC Design & Intro. to ADCs © 2010 Page 26
Example: ADC Spectral Tests
SFDR
SDR
SNR
Ref: (^) at Nyquist input,"W. Yang et al., "A 3 IEEE J - V 340_._ - of Solid mW 14 - - State Circuits, b 75-Msample/s CMOS ADC with 85 Dec. 2001 -dB SFDR
SNR loss due to clock jitter f
s
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 27
Summary
Effect of Clock Jitter on ADC Performance
- In cases where clock signal is provided from off choose a clock signal source with low enough jitter-chip have to
- On pico-chip precautions to keep the clock jitter less than single-second : -digit
- Separate supplies as much as possible
- Separate analog and digital clocks
- Short on-chip inverter chains between clock source and destination
- Few, if any, other analog-to-digital conversion non-idealities have
the same symptoms as sampling jitter:
- RMS noise proportional to input signal frequency
- RMS noise proportional to input signal amplitude
In cases where clock jitter limits the dynamic range, it’s easy
to tell, but may be difficult to fix...
Practical Sampling Issues
vIN vOUT C
M
- Switch induced noise due to M1 finite channel resistance
- Clock jitter (edge variation of 1 )
- Finite Rsw limited bandwidth finite acquisition time
- Rsw = f(Vin) distortion
- Switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 31
Practical Sampling Issues
vIN vOUT C
M
- Switch induced noise due to M1 finite channel resistance
- Clock jitter (edge variation of 1 )
- Finite Rsw limited bandwidth finite acquisition time
- Rsw = f(Vin) distortion
- Switch charge injection & clock feedthrough
Non-Linear Switch On-Resistance
( )^ (^ ) 0
,^1 2 1 1
Let us call @ =0^1
1
DS D triode ox GS TH DS DS^ D triode ON DS (^) V
ON ox GS th ox DD th in
in o o ox DD th ON o in DD th
I C W V V V V^ dI L R dV
R (^) W W C (^) L V V C (^) L V V V
R V R then R (^) W C (^) LV V
R R V V V
^
(^)
Switch MOS operating in triode mode:
Vin
C
M
VGS =^ ^1^ ^ VDD
VDD - Vin
EECS 247 Lecture 16: Data Converters- ADC Design © 2010 Page 33
Sampling Distortion
in DD th
out T V 2 1 V V in
v
v 1 e^
^
Simulated 10-Bit ADC & Sampling Switch modeled:
Ts/2 = 5 VDD – Vth = 2V VFS = 1V Results in HD2=-41dBFS & HD3=-51.4dBFS
Sampling Distortion
10bit ADC Ts/2 = 10 VDD – Vth = 2V VFS = 1V
Doubling sampling time (or ½ time constant) Results in: HD2 improved from - 41dBFS to - 70dBFS ~30dB HD3 improved from - 51.4dBFS to - 76.3dBFS ~25dB
Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior to a tolerable level
EECS 247 Lecture 16: Data Converters- ADC Design, Sampling © 2010 Page 37
Practical Sampling
Summary So Far!
2 2
12 B^2^ B
FS
C k T V
g (^) ON g (^) o ^1 (^) VDD V in Vth for go Cox WL VDD Vth
s
R B f C
- kT/C noise
- Finite Rsw limited bandwidth
- gsw = f (Vin) distortion
- Allowing long enough settling time reduce distortion due to
sw non-linear behavior
vIN^ vOUT C
M
EECS 247 Lecture 16: Data Converters- ADC Design, Sampling © 2010 Page 38
Sampling
Use of Complementary Switches
1B
1B
gon
gop
go goT (^) =gon (^) + gop
- Complementary n & p switch advantages: Increase in the overall conductance lower time constant Linearize the switch conductance for the range |Vthp|< Vin < Vdd - |Vthn|
EECS 247 Lecture 16: Data Converters- ADC Design, Sampling © 2010 Page 39
Complementary Switch Issues
Supply Voltage Evolution
- Supply voltage has scaled down with technology scaling
- Threshold voltages do not scale accordingly Ref: A. Abo et al, “A 1.5 1999, pp. 599. -V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May
EECS 247 Lecture 16: Data Converters- ADC Design, Sampling © 2010 Page 40
Complementary Switch
Effect of Supply Voltage Scaling
gon
gop
geffective goT (^) =gon (^) + gop
- As supply voltage scales down input voltage range for constant go shrinks Complementary switch not effective when VDD becomes comparable to 2xVth
1B
1B
