CSCI 4717 – Computer Architecture Fall 2006 Superscalar In-class Assignment
1. Identify the write-read, write-write, and read-write dependencies in the instruction sequence below by
entering each line pair with a dependency in the correct column of the table to the right. For example, if L1
and L4 had a write-write dependency (which they don’t), you would enter L1-L4 in the column labeled
“write-write”.
L1: R1 = 100
L2: R1 = R2 + R4
L3: R2 = R4 - 25
L4: R4 = R1 + R3
L5: R1 = R1 + 30
2. Rename the registers from problem 1 to prevent dependency problems. Identify references to initial
register values using the subscript 'a' to the register reference.
L1: R1b = 100
L2: R1c = R2a + R4a
L3: R2b = R4a - 25
L4: R4b = R1c + R3a
L5: R1d = R1c + 30
Questions 3 and 4 are based on the "in-order issue/in-order completion" execution sequence shown in the figure
below. Decode Execute Write Cycle
I1 I2 1
I2 I1 2
I2 I1 3
I3 I4 I2 4
I5 I6 I4 I3 I1 I2 5
I5 I6 I3 6
I5 I6 I3 I4 7
I5 8
I5 I6 9
3. Identify the most likely reason why I2 could not enter the execute stage until the 4th cycle. Will "in-order
issue/out-of-order completion" or "out-of-order issue/out-of-order completion" fix this? If so, which?
Since I2 and I1 are in different columns of the execution unit, it is unlikely that there is a resource conflict,
i.e., I2 is not waiting for I1 to finish using one of the CPU's resources. What is far more likely is that there
is a true data dependency here. In other words, the result of I1 is needed to execute I2.
True data dependencies cannot be fixed using out-of-order issue or out-of-order completion. Therefore,
there will be no speed up of I2 with respect to I1 by changing the issue sequence or output sequence.
write-read
*L2 – L4
*L2 – L5
L1 – L4
L1 – L5
write-write
*L1 – L2
*L2 – L5
L1 – L5
read-write
L2 – L3
L2 – L4
L3 – L4
L4 – L5
