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These lecture notes cover the concepts of space complexity, lemmas related to space complexity, reductions, and completeness. The notes include proofs and examples, focusing on log-space reductions and the nl-completeness of directed graph reachability.
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We assume that the input is read only, and that the output is write only, and we don’t count either as part of the memory (space) usage.
Lemma 1. If f and g are functions computable in DSP ACE(S(n)), then g◦f = g(f (x)) ∈ DSP ACE(S(exp(S(n)))).
Corollary 1. If f and g are functions computable in L = DSP ACE(log n) then g◦f ∈ L = DSP ACE(log n)
Suppose we first run a machine for f to compute f (x) on its output tape, and then use this same tape as the input to g. The output tape doesn’t count as memory used by f , and it doesn’t count as memory used by g, but it does count as memory used by a machine which computes g ◦ f using this approach. Thus, this approach may well use too much space. Instead, use two additional counters: one to store the position on the output tape of f , and one to store the position on the input tape of g.
Lemma 2. If any space S(n) ≥ log n algorithm runs for more than exp(S(n)) time, then it doesn’t terminate.
Proof. The number of configurations is at most exp(S(n)). If we run for more than the number of configu- rations steps, then we must be in the same configuration twice, and therefore will repeat the same sequence of steps forever.
Corollary 2. DSP ACE(S(n)) ⊆ DT IM E(exp(O(S(n)))) for S(n) ≥ log n.
Corollary 3. If f ∈ DSP ACE(S(n)) for S(n) ≥ log n, then |f (x)| ≤ exp(O(S(n))).
Returning to the simulation of g ◦ f : Simulate g(y) where we think of y = f (x), keeping track of the position i of the position of the input tape head for g. Every time that we need the value of yi, we compute f (x) from scratch until it outputs the ith^ bit. Then resume the simulation of g. Since we reuse the same memory for each simulation of f it uses a total of S(n) space. Simulating g uses space S(|f (x)|) ≤ S(exp(S(n))), and space O(S(n)) to keep track of the position of the tape heads. Thus, we conclude Lemma 1.
For languages A and B, a log-space mapping reduction from A to B, written A ≤mL B, is a function f ∈ L such that x ∈ A ⇐⇒ f (x) ∈ B. From Lemma 1, if A ≤mL B and B ∈ L then A ∈ L. Also from Lemma 1, if A ≤mL B and B ≤mL C then A ≤mL C.
Given a notion of reduction, we can defined a notion of completeness. Consider the language Directed Graph Reachability, DGR = {〈G, u, v〉 | there is a directed path from u to v in the graph G = (V, E), represented by an adjacency matrix}.
Theorem 1. DGR is N L-complete under ≤mL reductions.
Proof. First, DGR ∈ N L: We store in memory a vertex a ∈ V and maintain the invariant that along an non-rejecting computation path there exists a path in G from u to a. Begin with a = u. If a = v accept. Non-deterministically choose b ∈ V. If (a, b) 6 ∈ E reject, otherwise set a = b and continue. If we run for more than |V | steps, reject. This algorithm uses log n space for a, log n space for b, and log n space to count steps, for a total of O(log n) memory. If there exists a path in G from u to v, then there exists a path from u to v without any cycles of length at most |V |. When the algorithm non-deterministically chooses the vertices along this path it will accept. If the algorithm accepts, then the sequence of values for a must correspond to a path from u to v in G. Second, we must show that for all A ∈ L we have A ≤mL DGR: We will construct a graph where vertices correspond to configurations of a machine for A, u is the initial configuration, and v is a fixed accepting configuration, say with all tapes erased and in a specific accepting state; and where edges correspond to valid non-deterministic transitions between configurations. Formally, let M be a non-deterministic log-space TM for A (which erases it’s tapes, etc. before accepting), and let x by any input to M. V = set of all configurations of M on inputs of length n. |V | = poly(n) and each v ∈ V has an O(log n) bit representation. E = {(c 1 , c 2 ) | M can go from configuration c 1 to c 2 , on input x, in one step}. For each pair c 1 , c 2 of O(log n) bit configurations, using an O(log n) bit counter for the ith^ bit of x, we can compute whether (c 1 , c 2 ) ∈ E straightforwardly in log-space. The output is 〈G = (V, E), u, v〉 where u is the start configuration and v is the unique accept configuration. By construction (essentially) there is a path from u to v in G if and only if there is an accepting computation of M on input x if and only if x ∈ A.
It follow directly from Theorem 1 that N L ⊆ P. For any A ∈ N L, there exists f ∈ L such that x ∈ A ⇐⇒ f (x) ∈ DGR. Since f ∈ L, we know f ∈ F P. Therefore A ≤mp DGR and DGR ∈ P , so A ∈ P. L ⊆ N L ⊆ P ⊆ N P ⊆ P SP ACE. By diagonalization similar to the time hierarchy theorem, we know L ⊂ P SP ACE. We will show N L ⊂ P SP ACE, but we don’t know which of the other inclusions are proper.
Theorem 2 (Savitch’s Theorem). N SP ACE(S(n)) ⊆ DSP ACE(S(n)^2 ) for S(n) ≥ log n
Corollary 4. N L ⊆ DSP ACE(log^2 n)
Proof. From Theorem 1, we know DGR is N L-complete. Thus, if we give a DSP ACE(log^2 n) algorithm for DGR we can conclude that N L ⊆ DSP ACE(log^2 n).