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- Suppose we have a 16MB (2^24 bytes) memory that is byte addressable, and a 128KB (2^17 bytes) cache with 64 (2^6 ) bytes per block. a) How many total lines are in the cache?
b) If the cache is direct-mapped, how many cache lines could a specific memory block be mapped to?
c) If the cache is direct-mapped, what would be the format (tag bits, cache line bits, block offset bits) of the address? (Clearly indicate the number of bits in each)
d) If the cache is fully-associative, how many cache lines could a specific memory block be mapped to?
e) If the cache is fully-associative, what would be the format of the address?
f) If the cache is 4-way set associative, how many cache lines could a specific memory block be mapped to?
g) If the cache is 4-way set associative, how many sets would there be?
h) If the cache is 4-way set associative, what would be the format of the address?
Computer Org. (CS 1410) Lecture 26 Name :_____________________
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- Consider the demand paging system with 1024-byte pages.
CPU
Physical Memory
page 0
page 0 page 3
page 3
page 1
page 1 page 4
page 4
page 2
page 2 page 5
page 5
page 6
page 6
Process A
Process B
Frame Number
page 3 of A
page 5 of B
page 2 of A page 4 of B
page 5 of A
page 2 of B
page 0 of A
page# offset frame# offset
Running Process B (^) Frame#
Valid Bit 0 1 2 3 4 5 6
Page Table for B
Logical Addr. Physical Addr.
a) Complete the above page table for Process B.
b) If process B is currently running and the CPU generates a logical/virtual address of 2060 10 , then what would be the corresponding physical address?
- For a 32-bit address machine with 4 KB (2^12 bytes) pages and 4 byte page-table entries, how big would the page table be?
- How does a TLB (translation-lookaside buffer) speed the process of address translation?
Computer Org. (CS 1410) Lecture 26 Name :_____________________
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