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SPRING 2001
COMPUTER SCIENCES DEPARTMENT
UNIVERSITY OF WISCONSIN—MADISON
PH.D. QUALIFYING EXAMINATION
Computer Architecture
Qualifying Examination
Monday, February 5th 2001
3:00 – 7:00 PM
Room 115 Psychology
GENERAL INSTRUCTIONS:
- Answer each question in a separate book.
- Indicate on the cover of each book the area of the exam, your code number, and the question answered in that book. On one of your books list the numbers of all the questions answered. Do not write your name on any answer book.
- Return all answer books in the folder provided. Additional answer books are available if needed.
SPECIFIC INSTRUCTIONS:
Answer all of the following SIX questions. The questions are quite specific. If, however, some confusion should arise, be sure to state all your assumptions explicitly.
POLICY ON MISPRINTS AND AMBIGUITIES:
The Exam Committee tries to proofread the exam as carefully as possible. Nevertheless, the exam sometimes contains misprints and ambiguities. If you are convinced a problem has been stated incorrectly, mention this to the proctor. If necessary, the proctor can contact a representative of the area to resolve problems during the first hour of the exam. In any case, you should indicate your interpretation of the problem in your written answer. Your interpretation should be such that the problem is non-trivial.
1. Implementing an Interconnection Network Switch
Consider a simplified N-bit-wide 2x2 switch with two input ports and two output ports. Each input port j has inputs in_j_request, in_j_data<N-1:0>, and in_j_address. Each output port k has outputs out_k_request and out_k_data<N-1:0>.
In this problem ignore clocking and consider implementing the switch in combinational logic. If in_j_request is asserted then the switch should try to deliver in_j_data<N-1:0> to the output port specfied by in_j_address. Each output port’s out_k_request should be asserted if and only if an outgoing request is present.
(a) Implement the N-bit-wide 2x2 switch decribed above using gates (but not tri-state gates), encoders, decoders, and multiplexors.
(b) If the two input ports request different output ports, are both values delivered? Why or why not?
(c) Sketch out how you would build a 4x4 switch from several 2x2 switches. If the four input ports request distinct output ports, are all values delivered? Why or why not?
2. Predicated Execution
(a) What is predicated execution? Explain with an example.
(b) Mahlke, et. al., distinguish between two forms of predicated execution: full and par- tial. What is the distinction between the two, and what are the implications of the dis- tinction? Discuss the pros and cons of these two approaches to predication.
(c) What are the alternatives to predicated execution, and how do they achieve the objec- tives of predicated execution?
3. Single Chip Multiprocessors
As on-chip transistor resources have increased, computer architects have included more and more functionality on a chip, including functions that occupied multiple chips in a previous generation (e.g., floating point units and caches). Based upon these historical trends, it is becoming increasing obvious that before long architects will be building sin- gle chip multiprocessors.
(a) Discuss how the design of single chip multiprocessors is likely to be similar to tradi- tional multiprocessors. That is, how might the architectural/microarchitectural mech- anisms used in traditional multiprocessors be important to /relevant in single chips multiprocessors.
(b) Discuss how the design of single chip multiprocessors is likely to be different from tra- ditional multiprocessors. That is, what new architectural/microarchitectural mecha- nisms might be needed for single chips multiprocessors.
