Standard Timer Module (TIM) - Input Capture and Output Compare - Prof. Steven F. Barrett, Study notes of Microprocessors

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Revised: Aug 1, 2003

EE4390 Microprocessors

Lessons 19 - 22Standard Timer Module (TIM)

Revised: Aug 1, 2003

Standard Timer Module (TIM)• Fundamental Timing Concepts• The Standard Timer Module• Input Capture - measure signal parameters– system description– register description– programming• Output Compare - generate precision signals– system description– register description– programming

Revised: Aug 1, 2003

Standard Timer Module (TIM)Fundamental Timing Concepts (cont)

Signal characteristics

• Revised: Aug 1,
• Standard Timer ModuleFundamental Timing (cont)Free running counter• Timer Enable (TEN)• MCLK• prescalar• frc - TCNT• timer overflow (TOF)• timer overflowinterrupt (TOI)• frc examplespg

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Calculating ElapsedTime

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Standard Timer Module (TIM)Input Capture - measure signal parameters

-^ Input Capture - measure signal parameters–^ system description–^ register description–^ programming•^ General concept–^ capture value of free running counter when user-specified eventoccurs• rising edge, falling edge, any edge–^ calculate elapsed time between key events–^ EX] pulse length, pg 257-

Revised: Aug 1, 2003 Programming - Input Capture EX] Measure the period of a periodic signalconnected to input capture channel 2– Assume MCLK is 8 MHz– Set prescaler to divide by 4– Clock frequency to frc is therefore 2 MHz– Period: 0.

μs

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Programming - Input Capture

Revised: Aug 1, 2003

Programming - Input Capture

main-initializeTIMERINIT MEAS_PER .area test_1(abs).ORG^ $^

;User RAM at $ edge_1 FDB^

;reserve word for variable period FDB^

;reserve word for variable _main::BSR TIMERINIT

;timer initialization subr BSR MEAS_PER

;measure period DONE:^ BSA DONE

;Branch to self

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Programming - Input Capture

;-----------------------------------------------;Subroutine TIMERINIT: Initialize timer for IC2;;-----------------------------------------------TIMERINIT: CLR

TMSK

;disable interrupts LDX^ #REG_BASE

;load register base to X LDAA^ #TMSK2_IN

;load TMSK2 using index addr STAA^ TMSK2,X

;disable ovf, prescale= LDAA^ #TCTL4_IN

;conf IC2 for rising edge STAA^ TCTL4,X

LDAA^ #TIOS_IN

;select ch 2 for IC STAA^ TIOS,X

LDAA^ #TSCR_IN

;conf IC2 for rising edge STAA^ TSCR_IN,X

; enable timer, standard flag clr RTS^

;Return from subroutine

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Output Compare - generate precision signals

-^ generate precision signals based on key events–^ active low or high pulse–^ repetitive signal ofdesired frequency and duty cycle–^ pulse width modulation•^ key events

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Standard Timer Module (TIM)Output Compare - generate precision signals

Revised: Aug 1, 2003

Programming - Output Compare

Revised: Aug 1, 2003

Programming - Output Compare

;----------------------------------------;MAIN PROGRAM: This program generates a;1000 Hz square wave with a 50% duty cycle;on output compare channel 2.;----------------------------------------TMSK1^ =^

$008C^

;declare locations of registers TMSK2^ =^

$008D^

;declare locations of registers TCTL2^ =^

$^

;declare locations of registers TIOS^ =^

$^

;declare locations of registers TC2H^ =^

$^

;declare locations of registers TSCR^ =^

$^

;declare locations of registers TFLG1^ =^

$008E^

;declare locations of registers TMSK2_IN^ =^

$^

;disable TOI, prescale= TCTL2_IN^ =^

$^

;initialize OC2 toggle TIOS_IN^ =^

$^

;select ch2 for OC TSCR_IN^ =^

$^

;enable timer, normal flag clr