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- Instructions are bits
- Programs are stored in memory — to be read or written just like data
- Fetch & Execute Cycle
- Instructions are fetched and put into a special register
- Bits in the register "control" the subsequent actions
- Fetch the “next” instruction and continue
Processor Memory
memory for data, programs, compilers, editors, etc.
Stored Program Concept
Instructions:
- Language of the Machine
- More primitive than higher level languages e.g., no sophisticated control flow
- Very restrictive e.g., MIPS Arithmetic Instructions
- We’ll be working with the MIPS instruction set architecture
- similar to other architectures developed since the 1980's
Characteristics of Instruction Set
- Complete
- Can be used for a variety of application
- Efficient
- Useful in code generation
- Regular
- Expected instruction should exist
- Compatible
- Programs written for previous versions of machines need it
- Primitive
- Simple
- Smaller
Example of multiple operands
- Instructions may have 3, 2, 1, or 0 operands
- Number of operands may affect instruction length
- Operand order is fixed (destination first, but need not that way)
add $s0, $s1, $s2 ; Add $s2 and $s1 and store result in $s
add $s0, $s1 ; Add $s1 and $s0 and store result in $s
add $s0 ; Add contents of a fixed location to $s
add ; Add two fixed locations and store result
Addressing
- Memory address for load and store has two parts
- A register whose content are known
- An offset stored in 16 bits
- The offset can be positive or negative
- It is written in terms of number of bytes
- It is but in instruction in terms of number of words
- 32 byte offset is written as 32 but stored as 8
- Address is content of register + offset
- All address has both these components
- If no register needs to be used then use register 0
- Register 0 always stores value 0
- If no offset, then offset is 0
- Instructions, like registers and words of data, are also 32 bits long
- Example: add $t0, $s1, $s
- registers have numbers, $t0=9, $s1=17, $s2=
- Instruction Format:
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
Machine Language
- Decision making instructions
- alter the control flow,
- i.e., change the "next" instruction to be executed
- MIPS conditional branch instructions:
bne $t0, $t1, Label beq $t0, $t1, Label
- Example: if (i==j) h = i + j;
bne $s0, $s1, Label add $s3, $s0, $s Label: ....
Control
- A simple conditional execution
- Depending on i==j or i!=j, result is different
Conditional Execution
- Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18;
- Solutions? Why not?
- put 'typical constants' in memory and load them.
- create hard-wired registers (like $zero) for constants like one.
- MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4
- How do we make this work?
Constants
- simple instructions all 32 bits wide
- very structured, no unnecessary baggage
- only three instruction formats
- rely on compiler to achieve performance — what are the compiler's goals?
- help compiler where we can
op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address
R
I
J
Overview of MIPS
- Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4°$t beq $t4,$t5,Label Next instruction is at Label if $t4=$t
- Formats:
- Could specify a register (like lw and sw) and add it to address
- use Instruction Address Register (PC = program counter)
- most branches are local (principle of locality)
- Jump instructions just use high order bits of PC
- address boundaries of 256 MB
I^ op^ rs^ rt^16 bit address
Address Handling
MIPS Instruction Format
31 26 25 21 20 16 15 11 10 6 5 0 JUMP (^) JUMP ADDRESS
31 26 25 21 20 16 15 11 10 6 5 0 BEQ/BNE/J REG 1^ REG 2 BRANCH ADDRESS^ OFFSET
31 26 25 21 20 16 15 11 10 6 5 0 SW REG 1^ REG 2 STORE ADDRESS^ OFFSET
31 26 25 21 20 16 15 11 10 6 5 0 LW REG 1^ REG 2 LOAD ADDRESS^ OFFSET
31 26 25 21 20 16 15 11 10 6 5 0 R-TYPE REG 1 REG 2 DST SHIFT AMOUNT ADD/AND/OR/SLT
31 26 25 21 20 16 15 11 10 6 5 0 I-TYPE REG 1^ REG 2 IMMEDIATE DATA
- LW R2, #v(R1) ; Load memory from address (R1) + v
- SW R2, #v(R1) ; Store memory to address (R1) + v
- R-Type – OPER R3, R2, R1 ; Perform R3 ß R2 OP R
- Five operations ADD, AND, OR, SLT, SUB
- I-Type – OPER R2, R1, V ; Perform R2 ß R1 OP V
- Four operation ADDI, ANDI, ORI, SLTI
- B-Type – BC R2, R1, V; Branch if condition met to address PC+V
- Shift class – SHIFT TYPE R2, R1 ; Shift R1 of type and result to R
- Jump Class -- JAL and JR (JAL can be used for Jump)
- What are th implications of J vs JAL
- Two instructions
Instruction
- LW/SW/BC – Requires opcode, R2, R1, and V values
- R-Type – Requires opcode, R3, R2, and R1 values
- I-Type – Requires opcode, R2, R1, and V values
- Shift class – Requires opcode, R2, R1, and shift type value
- JAL requires opcode and jump address
- JR requires opcode and register address
- Opcode – can be fixed number or variable number of bits
- Register address – 4 bits if 16 registers
- How many bits in V?
- How many bits in shift type?
- 4 for 16 types, assume one bit shift at a time
- How many bits in jump address?
Instruction Encoding
