ECE 2030B Exam Solutions: Switch-level Design, Mixed Logic Reengineering, Boolean Algebra , Exams of Computer Science

The solutions to exam one for the computer engineering course ece 2030b, offered in spring 2009. The exam covers various topics, including switch-level design, mixed logic reengineering, boolean algebra, and karnaugh maps. Students are required to complete incomplete circuits, implement boolean expressions using specific gate types, transform boolean expressions for switch-level implementation, and derive simplified expressions using karnaugh maps.

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2012/2013

Uploaded on 04/08/2013

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ECE 2030B Computer Engineering Spring 2009
4 problems, 4 pages Exam One Solutions 4 February 2009
1
Problem 1 (2 parts, 20 points) Switch-level Design
Several incomplete circuits are shown below. Complete each circuit by adding the needed
switching network so the output is pulled high or low for all combinations of inputs (i.e., no
floats or shorts). Complete each circuit (pull down, pull up, or both) and write the expression if
one is not given. Assume both inputs and complements are available.
A D E
BC F
OutXOutY
A
B
C
D
E
F
A
B
C
F
E
A
BC
EF
OUTx =
(
)
(
)
FEDCBA โ‹…+++โ‹…
OUTy = FECBA โ‹…โ‹…โ‹…+ )(
pf3
pf4

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4 problems, 4 pages Exam One Solutions 4 February 2009

Problem 1 (2 parts, 20 points) Switch-level Design

Several incomplete circuits are shown below. Complete each circuit by adding the needed switching network so the output is pulled high or low for all combinations of inputs (i.e., no floats or shorts). Complete each circuit (pull down, pull up, or both) and write the expression if one is not given. Assume both inputs and complements are available.

A D E

B C F

OutX OutY

A

B

C

D

E

F

A

B

C

F

E

A

B C

E F

OUTx = A โ‹…( B + C ) +( D + E ) โ‹… F

OUTy = ( A + B โ‹… C )โ‹… E โ‹… F

4 problems, 4 pages Exam One Solutions 4 February 2009

Problem 2 (2 parts, 28 points) Mixed Logic Reengineering

For the following expressions, implement the Boolean expression using the specified gate type. Use correct mixed-logic notation. Do not simplify the expression. You may use multi-input gates. Minimize the total transistors (switches) required. When possible, use common subexpressions to reduce gate counts. Also determine the number of switches used in each implementation.

Part A (14 points) Implement A โ‹… ( B + C )โ‹…(( B + C )+ D + E )using only AND and NOT gates.

A B C

D E

Out

switches = 1 x 8t + 3 x 6t + 5 x 2t = 36t

Part B (14 points) Implement A + ( B โ‹… C + D )+ E โ‹… F using only NAND and NOT gates.

A B C D E F

Out

switches = (^) 1 x 6t + 3 x 4t + 4 x 2t = 26t

4 problems, 4 pages Exam One Solutions 4 February 2009

Problem 4 (2 parts, 30 points) Karnaugh Maps

Part A (12 points) Given the following Karnaugh Map, circle and list all the prime implicants for a product-of-sums (POS) expression, indicating which are essential. Derive the simplified POS expression.

1 X 1 0

A

A

B B

C

C

C

D

D D

prime implicants

essential? yes no

0

B + C

B + D

C + D

B + C + D

simplified POS expression ( B + D ) โ‹…( B + C ) โ‹…( C + D ) (โ‹… B + C + D )

Part B (18 points) For the following expression, derive a simplified sum of products expression using a Karnaugh Map. Circle and list all the prime implicants for a sum-of-products (SOP) expression, indicating which are essential.

Out =( B + D )โ‹…( A + B + D )โ‹…( A + B + C )

A

A

B B

C

C

C

D

D D

prime implicants

essential? yes no

B C

A B

A C D

A B D

simplified SOP expression (^) A โ‹… B + B โ‹… C + A โ‹… B โ‹… D