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Main points of this exam paper are: Substrate, Sheet Resistance, Making Integrated, Circuit Resistors, Ignoring Contact Effects, Value, Length
Typology: Exams
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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
Professor Oldham Spring 1999
Your discussion TA: r Allan Chang r Lily Tam
- This is a closed book exam, but you may use your page of notes. - Please do all your work on the pages of this exam. Ask if you need extra paper. - Full credit will be given only when you indicate the source of your answer, such as a table, graph, or calcula- tion. - Please write your name in the above space - Special notes: 1. SOME GRAPHS AND FORMULAS ARE GIVEN AS APPENDICES TO THIS EXAM. BE SURE TO LOOK THESE OVER. 2. SOME PARTS OF THE EXAM ARE GRADED WITH NO PARTIAL CREDIT. They are noted. You may wish to double check your answers on those parts. 3. ONCE IN A WHILE SOME EXTRA CREDIT IS POSSIBLE FOR CLEVER INSIGHT. Again, these places are noted. But we will not answer questions about these problems. Just be very clear in your work.
Problem 1 (20 pts.) Problem 2 (25 pts.) Problem 3 (30 pts.) Problem 4 (25 pts.) TOTAL (100 pts.)
first last
Yes, I have looked these over. (Check box)
Problem 1 (20 pts.)
a. [No partial credit] In a certain process, a thick layer of n-type silicon (doping = is created over a p-type substrate. It is to be used for the purpose of making integrated circuit resistors. What is the sheet resistance of this layer? (Units must be .)
b. Using the layers of (a), above, you need to make a resistor with value of. It is wide. What must its length be (ignoring contact effects)?
c. Someone properly points out to you that the layer in part a), though it is physically thick, is electri- cally somewhat thinner, because there must be a depletion layer at the n-p interface. (You are to ignore this in part a.) Suppose the doping in the p region is also (but acceptors instead of donors). At zero applied voltage between the n and p regions (i.e., in thermal equilibrium), just what is the net electrical thickness of the n-region? (Thickness minus depleted portion.)
2 μm 2 × 10 15 cm 3 ⁄
Ω ⁄square
200 KΩ 5 μm
2 μm
2 × 10 15 ⁄cm 3
( μm)
gate oxide
/
source (^) n+ polysilicon gate interconnect (^) /
drain
bulk interconnect
oxide
Four-mask layout and cross section of an integrated n-channel MOSFET.
L
L (^) dl.ff
d. Now we adjust the flat-band voltage (and thus the threshold voltage) with an ion implant just at the bottom of the gate oxide. We set the implant value to get a final threshold of 0.5 V. In testing the device we short source to body, i.e.,.
d.1) [No partial credit] What is of this device if we set?
d.2) Neatly sketch the I-V characteristics on the linear axes below for three cases: , and. Cover the range. Assume the electron mobility in the channel is. You must put a scale on the current axis. (Note that partial credit will only be possible if you very carefully show your work, including giving any formulas you are using before evaluation.)
V (^) Tn V (^) SB = 0
V (^) DSAT V (^) GS = 2 V
V (^) GS = 0.5 V , V (^) GS = 1 V V (^) GS = 2 V V (^) DS = 0 to 5 V 500 cm 2 ⁄Vsec
Drain Current
Drain-Source Voltage
Problem 4 (25 points)
A p-n junction capacitor is made in an integrated circuit with the cross-section as shown below. The p-region is
very heavily doped compared to the n-region (it is a p +n junction) and the n-region doping is. The
junction area is , or.
a) Make a sketch of the charge density (C/cm 3 ), the electric field (V/cm), and the potential versus for this structure at 5V reverse bias. The “graph paper” is provided on the page opposite. As part of the calcula- tion to prepare these graphs, please compute the following:
a.1) The built in voltage
a.2) The depletion width at 5V reverse bias
a.3) The peak electric field at 5V reverse bias
b) What is the small-signal capacitance at 5V reverse bias?
1 × 1014 cm 3 ⁄ 100 × 200 μm 2 10 –^4 cm 2 ×