Super Node - Engineering Electrical Circuits - Lecture Slides, Slides of Electrical Circuit Analysis

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Super Node/Mesh

Thevénin/Norton

OutLine

• ReIterate NODE & LOOP/MESH Analysis by

way of Examples

• SuperNode Method
• SuperMesh Technique
• Loops vs Meshes; describe difference
• Loop & Node Compared
• Introduction to Thevenin & Norton theorems

Node Analysis (find V by kCl)

1. Define a GND Node
2. Label all Non-GND nodes not connected to a Source; i.e., the UNknown Nodes
3. Write the CURRENT Law Eqns at the Unknown Nodes using Ohm’s Law; I = ΔV/R
4. Clear Fractions by Multiplying by the LCD

• Be sure to Include UNITS

5. Work the Linear Algebra to find Unknown Node Voltages

Example (On Board)

1. Define a GND Node Loop Analysis (find I by kVl)
2. Draw Current Loops or Meshes to

• NOT be Redandant
• Pass Thru ALL Circuit Elements

3. Write the VOLTAGE Law Eqns For each Loop/Mesh usingNodes using Ohm’s Law; ΔV=RI
4. Divide by Eqns by the LCM of the I’s

• Be sure to Include UNITS

5. Work the Linear Algebra to find Unknown Loop/Mesh Currents

Example (On Board)

ReCall Node (KCL) Analysis

• Need Only

ONE KCL Eqn

k

V V

k

V V

k

V

 The Remaining Eqns From the Indep Srcs

6 [ ]

12 [ ]

3

1 V V

V V = −

=

 Solving The Eqns

4 6 [ ] 1. 5 [ ]

2 ( ) ( ) 0 2 2

2 2 3 2 1 V V V V

V V V V V = ⇒ =

• − + − =

 3 Nodes Plus the Reference. In Principle Need 3 Equations...

• But two nodes are connected to GND through voltage sources. Hence those node voltages are KNOWN

Supernode cont.

• Apply KCL to the Surface

 Now Have 2 Equations in 2 Unknowns  Then The Ckt Solution Using LCD Technique

• See Next Slide

SUPERNODE

I S 4 0 6 12

− 6 +^1 +^2 + mA = k

V k

mA V

V 1 (^) − V 2 = 6 [ V ]

• The Source Current Is interior to the Surface and is NOT Required  Still Need 1 More Equation – Look INSIDE the Surface to Relate V 1 & V 2

Now Apply Gaussian Elim

• The Equations

(2) 6 [ ]

6 4 0 6 12

(1)

1 2

1 2

V V V

mA mA k

V k

V

− =

• − + =

 Mult Eqn-1 by

LCD (12 kΩ)

6 [ ]

2 24 [ ] 1 2

1 2 V V V

V V V − =

• =

 Add Eqns to Elim V 2

3 V 1 = 30 [ V ]⇒ V 1 = 10 [ V ]

V 2 (^) = V 1 − 6 [ V ]= 4 [ V ]

 Use The V-Source

Rln Eqn to Find V 2

SUPERNODE

I S

Illustration using Conductances

• Write the Node Equations
  • KCL At v 1

 At The SuperNode Have V-Constraint

• v 2 − v 3 = v (^) A  KCL Leaving Supernode

 Now Have 3 Eqns in 3 Unknowns

• Solve Using Normal Techniques







Example

• Find Io
• Known Node Voltages

 Now use KCL at SuperNode to Find V 3

V 2 (^) = − 6 V , V 4 = 12 V  The SuperNode V-Constraint

V 1 − V 3 = 12 V or V 1 = V 3 + 12 V

 Mult by 2 kΩ LCD, collect Terms to Find:

SUPERNODE = V 3 + 12

Dependent Sources

• Circuits With Dependent Sources Present No

Significant Additional Complexity

• The Dependent Sources Are

Treated As Regular Sources

• As With Dependent CURRENT Sources Must

Add One

Equation For Each

Controlling Variable

Numerical Example – Dep Isrc

• Find Io by Nodal Analysis
• Notice V-Source Connected to the Reference Node

 KCL At Node-2 ^ Sub^ I^ x^ into KCL Eqn

 Mult By 6 kΩ LCD

V 1 = 3 V

 Then I (^) o

2 −^1 + 2 − =

k Ix

V

k

V V

 Controlling Variable In Terms of Node Potential (^) k I V x (^) 6 =^2

0 6

2 3 6

2 − (^1) + (^2) − (^2) = k

V k

V k

V V

V (^) 2 − 2 V 1 = 0 ⇒ V 2 = 6 V

mA k

V V I (^) O 1 3

=^1 −^2 =−