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THE OUTLINE
- INTRODUCTION
- THE SPARC PROCESSOR
- The Modules
- Integer Unit (IU)
- The Register Window Concept
- Floating Point Unit (FPU)
- Coprocessor
- Instructions
- Traps
- THE SUPERSPARC PROCESSOR
- System Interconnect
- IU Capabilities
- FPU Capabilities
- Cache & Memory Organization
- CONCLUSIONS
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INTRODUCTION
- SPARC stands for S calable P rocessor ARC hitecture.
- SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II designs engineered at the University of California at Berkeley from 1980 through 1982.
- SPARC is a CPU instruction set architecture (ISA), derived from a Reduced Instruction Set Architecture (RISC).
- The SPARC architecture is a public property in the sense that the semiconductor manufacturers are encouraged to produce their own implementation of the SPARC architecture.
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THE SPARC ARCHITECTURE:
THE SUPERSPARC MICROPROCESSOR
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THE SPARC PROCESSOR
- The SPARC processor is divided into three parts:
- an Integer Unit (IU)
- a Floating-Point Unit (FPU)
- an optional CoProcessor (CP), each with its own registers. (32-bits wide).
- The SPARC processor can be in either of 2 modes:
- Supervisor mode: The processor can execute any instruction, including the privileged instructions.
- User mode: “User Application” programs will be executed in user mode.
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THE MODULES
Integer Unit
(IU)
Floating-Point
Unit
(FPU)
CoProcessor
(CP)
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THE MODULES
Integer Unit
(IU)
Floating-Point
Unit
(FPU)
CoProcessor
(CP)
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THE INTEGER UNIT (IU)
- Contains the general purpose registers and controls the overall operation of the processor.
- Executes the integer arithmetic instructions and computes memory addresses for loads and stores.
- Maintains the program counters and controls instruction execution for the FPU and the CP.
- May contain from 40 to 520 general-purpose 32-bit registers which corresponds to a grouping of the registers into 8 global registers and a circular stack of from 2 to 32 sets of 16 registers, known as register windows.
Integer Unit Docsity.com (IU)
THE REGISTER WINDOW CONCEPT
- Each instruction can access the 8-globals and a register window into the 24 registers.
- A register window comprises a 16-register set- divided into 8 in and 8 local registers- together with the 8 in registers of an adjacent register set, addressable from the current window as its out registers.
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THE ADVANTAGES OF USING
MULTIPLE WINDOWS
- Make very fast procedure calls as they avoid the need to save
a processor’s current in memory, further reducing off-chip traffic.
- Instead, the state variables are held in the current window,
and the next window is opened for the new procedure.
- A refinement on this idea in that the input and output
registers of adjacent windows overlap, allowing variables and parameters to be passed to the next process without physically moving data.
Integer Unit Docsity.com (IU)
THE SPARC’s CIRCULAR REGISTER
WINDOWS
- The additional registers are hidden from view until you call a subroutine or other function. Where other processors would push parameters on a stack for the called routine to pop off, SPARC processors just "rotate" the register window to give the called routine a fresh set of registers.
- The old window and the new window overlap, so that some registers are shared.
Integer Unit Docsity.com (IU)
THE COPROCESSOR
- The coprocessor instructions mirror the floating-point instructions ; - Load/store coprocessor, - Branch on coprocessor condition codes, - Coprocessor operate (CPop).
- Coprocessor operate instructions can execute concurrently with integer instructions.
- The coprocessor unit has its own set of 32-bit registers.
- The actual configuration of registers is implementation- dependent.
CoProcessor Docsity.com^ (CP)
INSTRUCTIONS
• Instructions fall into six basic categories:
- Load/Store
- Arithmetic/Logical/Shift
- Control Transfer
- Read/Write Control Register
- Floating-point Operate
- Coprocessor Operate
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A CASE STUDY:
The SuperSPARC Microprocessor
- A highly integrated superscalar microprocessor fully compatible with the SPARC v8 architecture.
- The processor contains
- an integer unit,
- double precision floating point unit,
- fully consistent instruction and data caches
- a SPARC reference memory management unit
- a dual mode bus interface supporting either the SPARC standard MBUS, or an interface optimized for connection to a companion second level cache controller chip. Docsity.com
SYSTEM INTERCONNECT
- The dual bus interface allows for systems to be designed either with or without an external cache.
- Processor modules, are constructed of the SuperSPARC processor and optionally an external cache built from synchronous SRAM and the SuperSPARC cache controller chip.
- The primary bus used by these modules is the “Level2” SPARC Mbus which is a 64-bit multiplexed, cache consistent bus interface specification.
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