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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Autumn Examinations 2010
Module Title: Computer Systems Design
Module Code: ELTR 8007
School: Electrical & Electronic Engineering
Programme Title: Bachelor of Engineering (Honours) in Electronic Systems Engineering - Award
Programme Code: EELES_8_Y
External Examiner(s): Dr. Andrew Donnellan, Dr. Paula O’Sullivan Internal Examiner(s): Mr. F. O Reilly
Instructions: Answer any THREE questions.
Duration: 2 Hours
Sitting: Autumn 2010
Requirements for this examination:
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
Q1 (a) Where do Structural, Control and Data hazards occur? Describe what they are and describe solutions/workarounds for each of them. [ 10 marks ]
(b) Explain how pipelining can create difficulties in memory access in a Von Neumann machine and how this can be tackled effectively. How is this solution implemented in modern micro-processors, (give examples). [ 10 marks ]
(c) Describe briefly two(2) of the following, using diagrams where appropriate.
Superscalar Execution, benefits and assisting techniques. Vector Processors and processing cores. Von Neumann Computer Design Principles
. [14 marks]
[ Total: 34 marks]
Q2 (a) In a paged memory management system, explain briefly the design process in deciding the size of pages, the numbers of pages, the number of page frames and page faults/replacements. [14 marks]
(b) Explain using diagrams, the UMA and NUMA architectures, justify which architecture is more common and give the term commonly used to describe it. [10 marks]
(c) A paging based virtual memory system has the following utilisations. CPU Utilisation 10% Paging Disk 90% Other I/O 10%
What do you think caused the low CPU utilisation? What steps if any do you think could be taken to improve CPU utilisation? [10 marks]
[ Total: 34 marks]
