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Synchronous Binary - Computer Engineering - Exam, Exams of Computer Science

Banaras Hindu University Computer Science

Main points of this exam paper are: Synchronous Binary, Minimum Number, Basic Gates, IncludeGlobal, Synchronous Binary, Basic Toggle, Enable Signal, Truth Table, Clearly LabelSignals, Multiplexor and Inverters

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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Cmpe 2030 A

Introduction to Computer Engineering

Quiz -II

May 7th, 1999

There are 7 questions and 10 pages including the cover sheet and two blank work sheets.

Please make sure that you have all of them. This examination is closed textbook. No calcula-

tors, class notes or any material is allowed!

1. Please show all of your work

2. State any assumptions you feel you have to make or ask for clarification

3. Keep in mind it is difficult to give partial credit without written material. Please make sure

you document any partial solutions.

4. Points are stated next to each problem. Use them to plan your work!

Name:_________________________________________________

Student Number:_________________________________________

Question Points Graded

1 8

2 8

3 6

4 6

5 8

6 68

7 8

Total 50

Discover Exams of Computer Science Banaras Hindu University

Partial preview of the text

Download Synchronous Binary - Computer Engineering - Exam and more Exams Computer Science in PDF only on Docsity!

Cmpe 2030 A

Introduction to Computer Engineering

Quiz -II

May 7th, 1999

There are 7 questions and 10 pages including the cover sheet and two blank work sheets.

Please make sure that you have all of them. This examination is closed textbook. No calcula-

tors, class notes or any material is allowed!

1. Please show all of your work

2. State any assumptions you feel you have to make or ask for clarification

3. Keep in mind it is difficult to give partial credit without written material. Please make sure

you document any partial solutions.

4. Points are stated next to each problem. Use them to plan your work!

Name:_________________________________________________

Student Number:_________________________________________

Question Points Graded 1 8 2 8 3 6 4 6 5 8 6 68 7 8 Total 50

1. Implement a synchronous binary counter that counts to ten. Use the minimum number of a

basic toggle cell shown below. In addition you have at your all of the basic gates. Assume

that the phi1 and phi2 clocks are available to all cells. Your design should include a global

Enable signal and a global CLR signal (active low) that works for all counters.

TE

CLR

Q

TE - Toggle Enable

CLR - Clear

3. This question is based on the following description of a priority encoder.

3 (a) List the inputs from highest to lowest priority order.

3 (b) Implement OUT1 and OUT0 using basic gates.

IN0 IN1 IN2 IN3 OUT1^ OUT0 Valid

0 0 0 0 X X 0

X 0 X 1 1 1 1

X 0 1 0 1 0 1

X 1 X X 0 1 1

4. Complete the timing diagram below for a single bit register cell constructed from a pair of

transparent latches.

phi

Input

Out

input output

phi

register

cell

6. Complete the following timing diagram. Assume initial values of signals are zero. Ignore

any propagation delays.

C C C C C C C C

S S S

phi phi

3-bit Synch Binary Counter

Binary Decoder

C

phi

7. Using 4:1 multiplexors shown below construct shift logic that will produce an output

( b3b2b1b0 ) that is computed as a right shift or left shift of two bits of the input ( a3a2a1a0 ).

Assume a zero fill for the values shifted into the output B. For example, a right shift of

1100 by 2 bits will produce 0011.Fill in the truth table to reflect the operation being per-

formed for each value of the select lines.

S0 S1 Operation 0 0 0 1 1 0 1 1

s s

(^0) a3 a2 a1 a

b3 b2^ b1^ b

4:1 Mux 4:1 Mux (^) 4:1 Mux 4:1 Mux

shift right shift left no shift

Synchronous Binary - Computer Engineering - Exam, Exams of Computer Science

Related documents

Partial preview of the text

Download Synchronous Binary - Computer Engineering - Exam and more Exams Computer Science in PDF only on Docsity!

Cmpe 2030 A

Introduction to Computer Engineering

Quiz -II

May 7th, 1999

There are 7 questions and 10 pages including the cover sheet and two blank work sheets.

Please make sure that you have all of them. This examination is closed textbook. No calcula-

tors, class notes or any material is allowed!

1. Please show all of your work

2. State any assumptions you feel you have to make or ask for clarification

3. Keep in mind it is difficult to give partial credit without written material. Please make sure

you document any partial solutions.

4. Points are stated next to each problem. Use them to plan your work!

Name:_________________________________________________

Student Number:_________________________________________

1. Implement a synchronous binary counter that counts to ten. Use the minimum number of a

basic toggle cell shown below. In addition you have at your all of the basic gates. Assume

that the phi1 and phi2 clocks are available to all cells. Your design should include a global

Enable signal and a global CLR signal (active low) that works for all counters.

TE

CLR

Q

TE - Toggle Enable

CLR - Clear

3. This question is based on the following description of a priority encoder.

3 (a) List the inputs from highest to lowest priority order.

3 (b) Implement OUT1 and OUT0 using basic gates.

IN0 IN1 IN2 IN3 OUT1^ OUT0 Valid

0 0 0 0 X X 0

X 0 X 1 1 1 1

X 0 1 0 1 0 1

X 1 X X 0 1 1

4. Complete the timing diagram below for a single bit register cell constructed from a pair of

transparent latches.

phi

phi

Input

Out

input output

phi

phi

register

cell

6. Complete the following timing diagram. Assume initial values of signals are zero. Ignore

any propagation delays.

C

C

phi

phi

7. Using 4:1 multiplexors shown below construct shift logic that will produce an output

( b3b2b1b0 ) that is computed as a right shift or left shift of two bits of the input ( a3a2a1a0 ).

Assume a zero fill for the values shifted into the output B. For example, a right shift of

1100 by 2 bits will produce 0011.Fill in the truth table to reflect the operation being per-

formed for each value of the select lines.